VerificationOnWeb (VoW)

In the midst of a cold winter across India, there is some good news for those SystemC enthusiasts. While some in the industry thought the SystemC is being slow in adoption, there has been a constant need for moving up in abstraction in designing electronic systems. Over the past several years several ESL experiments have been carried out by local semiconductor/system companies in India. Incase you are deeply involved in this silent storm, here is your opportunity to broadcast your work as part of The Indian SystemC User’s Group (ISCUG). Abstracts are due by mid-Feb. See details at: www.iscug.in and you may download the CFP (Call For Papers from: http://www.cvcblr.com/downloads/iscug_CallForContribution.pdf

See you at ISCUG!

Many users find the factory feature in UVM as quite satisfying and easy to use and believe callbacks are not needed in UVM. However callback is a popular design pattern in software domain (see: http://stackoverflow.com/questions/946834/is-there-a-design-pattern-that-deals-with-callback-mechanism).

It is infact one of the very nice things that came from VMM to UVM. Though it is not that often used in UVM as in VMM, there are some pertinent use cases that makes the callbacks very handy in UVM as well. For instance consider a recent customer requirement that we handled:

How to terminate Testcase on Max Error Count Reached?

Of-course UVM has this support, but little “hidden” (see http://www.cvcblr.com/blog/?p=203 for similar stuff on VMM). You use the function:

set_report_max_quit_count(2); // Quit after 2 errors

However in the context of “phasing” this “terminates/interrupts” the phasing rather “abruptly”. While the UVM developers believe this is fine as default behavior we see more and more users would rather have the “report_phase” execute even in such cases. This helps in having a comprehensive display of test failures, status etc.

The good news though is that such usage has been “predicted” by UVM (was present in VMM as well, infact with very similar use model of pre_abort).

The uvm_component base class has a pre-defined callback named pre_abort – its documentation is below:

umv_component::pre_abort()

Function: pre_abort This callback is executed when the message system is executing a <UVM_EXIT> action. The exit action causes an immediate termination of the simulation, but the pre_abort callback hook gives components an opportunity to provide additional information to the user before the termination happens.

 

So in our case we added:

function void custom_reporter();
  uvm_report_server server;
  `uvm_info (get_name, "Custom reporter..", UVM_MEDIUM);
  server = uvm_report_server::get_server();

  if ((server.get_severity_count(UVM_ERROR) +
       server.get_severity_count(UVM_FATAL)) > 0)
       fail_banner();
  else if (server.get_severity_count(UVM_WARNING) > 0)
       warning_banner();
  else
       pass_banner();
endfunction

function void pre_abort();
  custom_reporter();
endfunction

function void report_phase(uvm_phase phase);
  super.report_phase(phase);
  custom_reporter();
endfunction

Notice that we used a custom System Verilog function named custom_reporter and called it in the callback pre_abort. What is also shown above is that it can be shared by regular route – i.e. the report_phase.

In case you want to see a full working example, contact us via info@cvcblr.com and we would be glad to assist.

Have fun verifying with SystemVerilog, UVM & VMM and in case you need to get trained on any of these, check out: http://cvcblr.com/trainings

As noted in our recent blog article http://www.cvcblr.com/blog/?p=362 UVM is the first genuine step in the industry towards verification inter-operability. But it has a long way to go before all the VIPs get migrated to UVM – if they do. So there is a strong need to leverage on existing code base such as VMM, OVM & UVM.

Below is a code snippet that shows how we can use both VMM & UVM messaging schemes in same env/code base. As such the code is not magic, is it? But do watch below for the real MAGIC..

If not for the inter-op kit, the above code would spit the messages from 2 different schemes and make it very hard for end user to keep track, customize etc.

With UVM & VMM loggers being separate and not “inter-operating” the following user issues may arise:

1. Different formatted messages coming at different lines, making it hard, ugly to read, analyze

2. Complicating data-mining of log files as there are 2 different formats now in same log file

3. Error, Warning counts distributed leading to unreliable FAIL/PASS detection

4. Any customization done by user on formatting needs to be done multiple times

5. Sending to different log files not as easy as it involves 2 different base classes now!

Again there are more, let’s get solutions on the table. Here comes the MAGIC: With VCS, try:

The log file now combines the `vmm_note into `uvm_info “magically” and unifies it for the users!

There is much more to this inter-op kit, see: http://www.vmmcentral.com/uvm_vmm_ik/ 

Enjoy UVM and more..

As industry gets ready for adopting UVM with SystemVerilog, there are several practical combinations that come to the fore. One of the important concerns is about the existing code base/VIPs that can be “reused as-is”, yet benefit from various UVM features. For instance consider a VMM based VIP being plugged into a new UVM based env. Several user requirements/expectations arise:

1. Can the UVM & VMM co-exist in same simulation?

2. Can we leverage on single messaging scheme – instead of both `uvm_error & `vmm_error counting on their own, how do we unify them?

3. Can UVM phasing control/synchronize the vmm_xacotr::start/stop_xactor?

4. How does the UVM-Objection work with VMM-Consensus?

5. How do we talk from VMM-channel to UVM components and vice-versa?

6.How does the UVM ACTIVE/PASSIVE mechanism control VMM xactors underneath?

7. Does UVM config mechanism affect the VMM, if yes, how, if not then what do we do?

I am sure there are more. But just enough to get you worried! Thankfully the problem seems to have been acknowledged by the EDA vendors and potential solutions have started emerging. For instance the recently released VMM/UVM inter-op kit from Synopsys is at: http://www.vmmcentral.com/uvm_vmm_ik/

Another common requirement from many customers is the ability to mix multiple modeling & verification languages with UVM. Cadence recently donated its version of UVM ML (Multi-Language) to Accellera for potential extension. This contains UVM-SystemC via TLM 2,0 and UVM-e for integrating IEEE 1647-E based eVCs to UVM. Though the industry has publically seen only Cadence’s Specman supporting IEEE 1647-E language, if John’s ESNUG were to be trusted (why not BTW?, see: http://www.deepchip.com/items/0495-02.html), it may be soon that all major vendors release E-support.

As noted in our recent blog, http://www.cvcblr.com/blog/?p=361 the upcoming 2012 year seems to be quite interesting for Verification technologies.

Many articles, discussions have, in the last few years declared the most powerful verification language, IEEE-1647, the E-language as “dead” in favor of SystemVerilog. While it is very clear “SystemVerilog” is step-up from Verilog and hence is an easier next step for Verilog/HDL based verification folks, it is far from replacing well established, and still growing capabilities of E – arguably the most powerful language to do verification of HDL designs.

With recent surge in Specman based jobs especially in India we were curious to see what’s happening. Here is what we found:

New Project starts with Specman

• To give first hand information, we at CVC (www.cvcblr.com) have recently started a customer verification project, from scratch using Specman to verify a new RTL design block.
• We also heard from Singapore that they have interns starting their projects in Specman. From industry/ecosystem point of view, internship is generally for future projects especially if they are on advanced topics.
• Specman based co-verification project recently done at TI India, see brief at: http://in.linkedin.com/pub/karthikeyan-b/19/a21/642 
• IEEE 1647-2011 updates: http://www.cvcblr.com/blog/?p=333 

The Job scenario/market

Most of the verification jobs in recent times have asked for Specman and/or SystemVerilog experts. Given the history of Specman in India it is natural to find more Specman engineers though lot many engineers are getting trained and deployed in SystemVerilog, our VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) training classes are selling hot cakes for the last 4 years!

What is really interesting is over the last few weeks there has been a sudden increase in Specman aware engineers from various Deisgn service providers in India. This is a very clear change in trend compared to last few years. Also we have more training queries coming to CVC on Specman/eRM/UVM-e – mostly from experienced engineers; another indicator of the sudden market change.

More than just Cadence/Specman supporting E?

Perhaps this would be the single most reason why many believe E is/was dying – it is a single vendor, but based on John Cooley’s time trusted ESNUG article, that maynot be true anymore, see:

Subject: Reader seeks user's reviews of SNPS/MENT support for Specman "e"

http://www.deepchip.com/items/0495-02.html

Also his previous post on related topic: http://www.deepchip.com/items/0488-05.html 

So at the close of 2011, the “Badshaah/King of Functional Verification language – IEEE-1647 is perhaps rejuvenating and coming stronger into 2012!

Technical background information

Perhaps the most recent one on technical front is the proposed UVM ML – Multi-language donation from Cadence to Accellera, see: http://www.uvmworld.org/contributions-details.php?id=98&keywords=UVM_ML 

In case you need deep technical articles.papers/webinars on this, see:

IEEE 1647-2011 updates: http://www.cvcblr.com/blog/?p=333 

E vs. SV technical comparison: http://www.cadence.com/rl/Resources/conference_papers/Apples_versus_apples_HVL_cp.pdf 

Webinar on Specman vs. SystemVerilog: http://www.cadence.com/Community/blogs/ii/archive/2011/09/21/webinar-seeks-to-end-the-debate-e-or-systemverilog.aspx

Join IEEE-DASC webinar for free at: https://www1.gotomeeting.com/register/450027193 

It is often a dream for many engineers in India to be part of IEEE committees, groups & associations and most of us feel proud about it. Here is your opportunity to take this to next step – you could well be developing, participating in next generation standards with special focus on India specific requirements too. Learn all about what it takes to participate in these activities in this hour long webinar for free @ https://www1.gotomeeting.com/register/450027193

Title: IEEE Design Automation Standards in India
Date: Tuesday, September 27, 2011
Time: 8:00 PM – 9:00 PM IST

For instance in the VLSI/EDA field there are several active standards such as:

•IEEE 1800 – SystemVerilog

•SV-AC assertions

•SV-EC – enhancements/TB

•Accellera VIP TSC – UVM

•IEEE 1647 – E language

•IEEE 1800 – PSL

•IEEE 1076 – VHDL

•IEEE 1801 UPF/Low Power

•IEEE 1666 SystemC

With the overwhelming marketing buzz around the modern day verification languages such as SystemVerilog and methodologies such as VMM, OVM, UVM etc. I at times feel sorry for those real soldiers of the Verification army – who carry out most of the verification execution as they are left behind a lot untouched by these “happening stuff”. For them all it matters is “Now that I have a failure, how soon can I narrow down” the same?

In an earlier article inTeamCVC blog, we explored the amount of debug that goes on in the industry, see: http://www.cvcblr.com/blog/?p=93 

Yet, the amount of investment that goes into debug automation is not as much as it should really be – partly the users are to blame – they do NOT often speak out LOUD asking for those “right” features with their vendors.

For a change, this time at SNUG India 2011 some of the audience questions were specifically targeted at this exact Debug menace. Few samples for those who missed it out:

• During Gate Level simulations I see failures say timing violations. How do I correlate the log/console to VPD and the source code – it is pretty much manual and takes way too much time.
• The answer lies with some of the advanced capabilities being developed as you could see in: http://www.vmmcentral.org/vmartialarts/category/debug/ 
• Many modern day waveform viewers provide a nice automation to link these automatically, ask you vendor for more

Amit Sharma did a commendable job in running like the recently introduced Duronto Express of Indian Railways: http://en.wikipedia.org/wiki/Duronto_Express in covering a whole of VCS/DVE/VIP updates in his tutorial. Many wondered if the audience were able to cope up, but surprisingly there were so many involved audience queries that proved such speculations wrong by miles!

Another interesting Debug related query was to do with the Protocol Analyzer feature that Amit introduced and its applicability to custom interfaces. Interestingly the same has been discussed as recently as last week in Accellera’s UVM extensions to add more callbacks to the UVM 1.1 to allow extended transaction recording. If you want to contribute to the same, join us at: http://www.accellera.org/activities/vip 

It will be interesting to see what the debug focused EDA companies like SpringSoft, and the new EDA kid Vennsa have to offer in this space.

Last week at SNUG India, LSI presented a good paper on the topic of Functional Coverage reuse (See: http://www.synopsys.com/Community/SNUG/India/Pages/Abstracts.aspx?loc=India&locy=2011#TA1)

Challenges and Approaches for Functional Coverage in SOC Verification Environments
Manikandan Subramanian, Ron Jacob, Sasidhar Dudyala, Srishan Thirumalai [LSI]

This paper describes the complexity in using block level functional coverage at top level and pitfalls and approaches to aid reuse. This also describes controllability on coverage infrastructure from block level to SOC level and how UVM-EA helped in building the layered testbench infrastructure that can be reused.

What I really liked about this is the level of maturity that the SystemVerilog adoption that this paper indicates in India – while functional coverage is one of the top few powerful features in System Verilog, its adoption has been traditionally slower than what we wished. Especially with the boatload of features, knobs/options to control/fine tune, it is clearly one of those features that is waiting to be explored in greater detail. In this paper Ron laid out a nice architecture for “coverage reuse” across levels of verification. The architecture he & his team proposed can be captured into 3 classes:

• Config class – to configure “How much do you want”
• Coverage class – to capture “what and all you want”
• Coverage collector class – to sample the coverage points

In a way the last 2 points have been stressed by VMM for years, and we at TeamCVC have been recommending it to our customers for years.

Specifically during our popular System Verilog training sessions such as VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) we compare this to an athletic race and describe how the “field meters” placed/planted in the filed actually measures the speed while the runners/athletes simply RUN RUn & RUN! 

Now compare this to a classical VMM environment:

The environment with all the components form the “field” while the “transactions” that flow through match the real “athletes”. It makes a lot of sense to plant the “measuring meters” (in this case the “coverage collectors and the coverage models” away from the actual transactions.

This is what Ron’s team experienced too. Though there are some ACC technologies such as ECHO in VCS that traditionally worked better (see: http://www.cvcblr.com/blog/?p=9) with transactions “embedded with covergroups”, VCS’s ECHO has come a long way and has supported VMM style covergroups as well.

The next big challenge that Ron addressed was the “reusability” and need to “control” the amount of coverage at System Level from block level. He had several good guidelines for the users, recommend highly to take down his paper and keep it handy at work! While some of the “sample_cov” overriding can be better done using SystemVerilog 2009 updates to built-in sample() function, a lot needs to be still done. For instance how do we override a full coverage model/covergroup/coverpoint/bins/cross etc. at System Level?

Ron’s approach was to add disable bits – yes, better than not having it, but it doesn’t scale up. Several years back Vera added such AOP/OOP style extensions to covergroups, but due to slow user adoption, this was never ported to SystemVerilog. Talk to Arturo Salz – friendly known as the “Father of Vera HVL” by many if you are interested.Basically the extensions are to allow things like:

• Add extra coverpoint/bin/cross
• Delete/drop a block level coverpoint/bin/cross
• Re-define the entire covergroup etc.

Now – where do we go from here – IEEE-SA invites sincere participation from end-users to set directions, drive language features/enhancements via active participation. See: https://mentor.ieee.org/stds-india/bp/StartPage to know more.

If you’ve missed being at SNUG India DCE 2011 – you’ve truly missed out the high spirits of a great ambience, great food and even greater freebies flowing in from all the participating companies – ranging from bags, pens, mugs, Android Phones, quick reference guides (SVA, UVM), Apple iPods, iTouch, and believe-it-or-not – the all new iPhone4 and of-course the best of all, the popular and most useful SystemVerilog books in the earth: SystemVerilog Assertions, 2nd edition (with IEEE 1800-2009 updates), Pragmatic Approach to VMM adoption and the PSL, IEEE 1850, now part of VHDL- 1076-2009.

TeamCVC’s booth was naturally focused on our core strength, some of the most popular Advanced Verification trainings in India and soon more globally too:

Given the vibrant ecosystem with 22+ participating companies setting up their booths, the ambience was amazing, electrifying and something that Leela Palace “GRAND Ballroom” was literally struggling to cope-up with. There were more than dozen folks mentioning it during the day:

Man, this is crazy, next year perhaps they should find a bigger place

And some suggestions were out for free from some audience too (if Synopsys wants to take tips ):

• ITPL convention centre
• Palace Grounds: http://en.wikipedia.org/wiki/Bangalore_Palace

Coming back to the 2011 event, the attendance at CVC booth was way above average, given the ideal location that one could have asked for – just right at the entrance and opposite to the “most happening” place in the DCE – i.e. the SNUG Prize booth – after all the iPhone/iPad’s were being handed out there, where else would you be?

Here are users eagerly waiting to hear “Who won the iPod” man..

At CVC we strongly believe that it is our “employees” that make the brand TeamCVC so unique and exclusive. With innovative business model that beats the attrition – we have a well established flow (See for our EIC at www.cvcblr.com/trainings) through which we are able to churn out VLSI professionals from fresh B.E. & M.Tech graduates – many fresh from their college. Here is our young army of VLSI folks all raring to go at problems that are just aptly being demonstrated at places such as SNUG!

And what is a better way to reward our TeamCVC booth attendees than providing them free books, calendar, SVA Quick reference guide and an invitation to join the IEEE-SA India initiative https://mentor.ieee.org/stds-india/bp/StartPage

Congratulations to all the winners and thanks for your continued patronage. Together WE can make the Indian VLSI ecosystem the BEST in the world!