Playing around debugging some complex assertions in Qeusta? Here are some tips:
1. Use vsim –assertdebug
2. Add –novopt for trivial code containing assertions + stim alone as otherwise many signals get optimized away. On real designs, perhaps you are better off with +acc* (Read doc for more)
3. Once the GUI comes up, the assertions are not [...]
Archive of entries posted by admin
Fun with Assertion Debugger in Questa – few tips
SystemVerilog OVM’s apply_config_settings – why & were?
Arayik Babayan, a friend of mine from Armenia asked me what is the use of “apply_config_settings” in OVM. As you may be aware SystemVerilog is a flexible language that can be used for building highly configurable and scalable verification environments. OVM adds a great deal of capabilities on top of plain “system verilog” to make [...]
Dealing with SystemVerilog constraint solver failures – the Questa way
… Tuesday Technote on Solver Debug, Jijo PS, Srini TeamCVC www.cvcblr.com
Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that [...]
Vibrant VMM becomes even better at SNUG India 2010
…Reflections from core engineering team of CVC – fresh from SNUG India 2010
Jijo PS, Thirumalai Prabhu, Kumar Shivam, Avit Kori, Praveen & Nikhil – TeamCVC www.cvcblr.com
2010 has been a great year so far for us the verification community in India – with constant news of fresh hirings, new project starts etc. For us at CVC [...]
ISA 2009-11 India Semiconductor Market Update – useful for many
Recently Dr. M M Pallam Raju, Honorable Minister of State for Defense, Government of India,
released ISA-Frost & Sullivan 2009-11 India Semiconductor Market Update. Here are excerpts from his speech during this release:
To face tomorrow, the Indian semiconductor industry has to rise to meet the challenges from other Asian countries and aid in developing the [...]
UVM gets better with a complete Reference Flow
If you have all been waiting for the UVM booth @ DAC, here is more to cheer about – a new “UVM reference flow/kit” is being donated (Apache/Limited GPL license) to the UVM community. For a change, we now have “true reference verification kit” that’s openly available to download, try it on any SystemVerilog simulator [...]
Verification pioneers do it again – welcome to Advanced Specman
Srinivasan Venkataraman, Chief Technology Officer, CVC Pvt Ltd (www.cvcblr.com)
TeamSpecman representatives for this Blog interview: Kishore Karnane, Adam Sherer, Hannes Froehlich, and Ariel Melchior
During recent ClubT India session I met the famous “TeamSpecman (www.twitter.com/teamspecman )” to see what’s new about Specman/e and general verification roadmap from them. To my pleasant surprise they offered much more than [...]
Pre-DAC round-up of Verification technologies
Given the business climate and local commitments, it is hard for me to be at DAC. But with keen focus on Verification it is kind of important for CVC (www.cvcblr.com) to share our thoughts on fresh ideas/technologies on Verification that are being demo-ed at DAC-2010 (www.dac.com). Leaving the BIG-3 out (I hope to blog about [...]
CFV + SystemVerilog basics
Title: CFV + SystemVerilog basicsLocation: www.cvcblr.comLink out: Click hereDescription: SystemVerilog basics.
Look at SVB portion from this profile:
http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf
This is intended mainly for FPGA designers, so the focus will be building fundamentals than building complex OOP testbench.Start Date: 2009-12-8End Date: 2009-12-9
Verification Using SystemVerilog (VSV)
Title: Verification Using SystemVerilog (VSV)Location: www.cvcblr.comLink out: Click hereDescription: Our popular corporate training on SystemVerilog for Verification. Details at:
http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdfStart Date: 2009-12-5End Date: 2009-12-7