At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: http://www.goo.gl/BKuNEd ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of “how verification shall be effectively carried out”, the next level of “What defines my verification space” has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will look at most (if not all, and maybe more) of the predecessors to define the future language for “Test Specification”.
1. Mentor’s inFact has a graph based language (http://www.mentor.com/products/fv/infact/) and a nice GUI around it.
2. Breker Trek (www.brekersystems.com) – one of the first EDA companies to promote Graph based verification. Breker strongly advocates use of Graphs for stimulus-coverage-checking – all 3 in one “scenario model”. To keep things true and open to our readers, CVC has been an official representative for Breker in India for few years by now.
3. Vayavya labs (http://vayavyalabs.com/technology/socx-verifier/) has a SOCX-Specifier that captures the scenarios and spits out SystemVerilog classes (a la UVM).
4. Cadence’s vPlan (extension to e) http://www.cadence.com/Community/tags/vManager/default.aspx – one of the earliest solutions in this space, has been in production use for many years at customer projects. Basically captures the plan-2-test-2-results flow in a XL form and/or vPlan file (ASCII) format. Allows teams to collaborate in a geographically distributed team by providing a common dashboard of the verification status.
5. SNPS VMMPlanner – http://news.synopsys.com/index.php?s=20295&item=122582 It also has a proprietary extension to SV known as HVP – Hierarchical Verification Plan.
6. CVC’s Assertion Driven Test Synthesis (www.cvcblr.com). As part of CVC’s Verification consulting engagements, we use an internal, time-tested approach to define the scenarios in an extended SVA-like syntax. The “test intent” is captured via SVA-like syntax and then our services team converts that to tests+checkers+scoreboard+coverage as per customer need on their chosen language & methodology. Contact srini <> cvcblr.com for more.
7. Bluespec’s BSV www.bluespec.com – not really a test specification language, rather a rule-based specification language built on top of SystemVerilog syntax. Not sure if they eye this new language development as a good opportunity to donate their language, but we at CVC believe this will be a good anecdote to learn from.
8. SV’s own randsequence – a less known, less powerful feature of SystemVerilog called “randsequence” supports BNF style productions to specify the test-flow. Not very popular, though a detailed look by the proposed committee is worth, as we feel.
Maybe there are few more solutions around that we haven’t captured here, please do send the details to me via email (srini<>cvcblr.com), we will consider adding them here soon.
Now to conclude/wrap-up this (long) post, here are some abbreviations for this next generation language – surely a lot more names can be considered, a starting list:
. TSL – Test Specification Language
. VSL – Verification Space/Specification Language
. GSL – Graph/Goal Specification Language