All posts by TeamCVC

SystemVerilog Soft constraints usage in `uvm_do_with macro

Recently we were asked a good & interesting question:

  • How do I use “soft constraint” in the macro `uvm_do_with? What would be the syntax?

I say this is a good & interesting b’cos of 2 things:

1. The SV LRM doesn’t give an explicit example for this (it is fine, not that it should, LRM is not a textbook)

2. The use case should be considered (This specific user had a good need – for automatic coverage closure – or ACC).

Now quickly jumping to solution, based on our SystemVerilog 2012 tutorial that our CEO Ajeetha delivered at IIT Mumbai earlier in 2014 (, here is a code snippet:


For those who need a quick background on what are soft constraints, see: 

Now with 3 major EDA vendors supporting this syntax, you should leverage on this more!

Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at:

Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:

  bit [7:0] msb_vec, lsb_vec;

msb_vec[7] = lsb_vec[0];
msb_vec[6] = lsb_vec[1];

// …

While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:

  msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic

But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator:

$display (” msb_vec: %b reverse: %b”, msb_vec, { << {msb_vec} } );

If the array was unppacked, there is a built-in array.reverse() available.

One of the good things about the modern, social media is we all stay connected atleast virtually – no matter where our careers take us to. In this case he is currently at Ahmedabad, Gujarat, India. So do feel free to contact us via for any SystemVerilog related help!

Test Specification Language – the past, present and the future

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of “how verification shall be effectively carried out”, the next level of “What defines my verification space” has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will look at most (if not all, and maybe more) of the predecessors to define the future language for “Test Specification”.

1. Mentor’s inFact has a graph based language ( and a nice GUI around it.


2. Breker Trek ( – one of the first EDA companies to promote Graph based verification. Breker strongly advocates use of Graphs for stimulus-coverage-checking – all 3 in one “scenario model”. To keep things true and open to our readers, CVC has been an official representative for Breker in India for few years by now.


3. Vayavya labs ( has a SOCX-Specifier that captures the scenarios and spits out SystemVerilog classes (a la UVM).


4. Cadence’s vPlan (extension to e) – one of the earliest solutions in this space, has been in production use for many years at customer projects. Basically captures the plan-2-test-2-results flow in a XL form and/or vPlan file (ASCII) format. Allows teams to collaborate in a geographically distributed team by providing a common dashboard of the verification status.


5. SNPS VMMPlanner – It also has a proprietary extension to SV known as HVP – Hierarchical Verification Plan.


6. CVC’s Assertion Driven Test Synthesis ( As part of CVC’s Verification consulting engagements, we use an internal, time-tested approach to define the scenarios in an extended SVA-like syntax. The “test intent” is captured via SVA-like syntax and then our services team converts that to tests+checkers+scoreboard+coverage as per customer need on their chosen language & methodology. Contact srini <> for more. 

7. Bluespec’s BSV – not really a test specification language, rather a rule-based specification language built on top of SystemVerilog syntax. Not sure if they eye this new language development as a good opportunity to donate their language, but we at CVC believe this will be a good anecdote to learn from.

8. SV’s own randsequence – a less known, less powerful feature of SystemVerilog called “randsequence” supports BNF style productions to specify the test-flow. Not very popular, though a detailed look by the proposed committee is worth, as we feel.

Maybe there are few more solutions around that we haven’t captured here, please do send the details to me via email (srini<>, we will consider adding them here soon.

Now to conclude/wrap-up this (long) post, here are some abbreviations for this next generation language – surely a lot more names can be considered, a starting list:

. TSL – Test Specification Language

. VSL – Verification Space/Specification Language

. GSL – Graph/Goal Specification Language

Which SystemVerilog LRM do you refer to?

As we get to the end of an eventful 2013 and look forward to a great 2014, TeamCVC is at Manipal, a beautiful coastal town in the West coast of India. Surrounded by Arabian sea coast on one side and Western Ghats on the other, this is the ideal place for a peaceful research center and it is no co-incidence that the famous Manipal University is housed here.

Coming to this town and conducting a 10-day boot-camp on SystemVerilog and UVM has been a pleasure so far as we have a young, talented, enthusiastic set of attendees. One thing that we continuously get asked during our VSV training sessions is – which SystemVerilog LRM to refer to? While the Google search reveals several PDFs, it gets quite confusing to a newcomer which one to pickup and refer to. In the past it used to be the due to “lack of reliable, legal reference” as the IEEE LRM was available at a cost. However the IEEE 1800-2012 LRM got released for free of cost, thanks to the IEEE GIT program. So go ahead and get a legal, personal copy of the SystemVerilog LRM for free from:

The added benefit of this updated LRM is that you also are ready embrace the latest features of this ever expanding language. As a tailpiece information, TeamCVC is delivering a half-day tutorial at IIT Mumbai as part of VLSI Design Conference 2014, so join us on Sunday, Jan 15th at IIT Mumbai if you want to get latest SV 2012 features explained with CVC’s renowned quality trainers!



Is your RTL Linter makes you find needle in the haystack? Here is a smarter approach!


Static design verification through thorough RTL analysis started several years ago, with early stage ones simply being “linters” and the later, advanced ones combining some of formal techniques as well. One of the most common complaints by RTL teams while using linters is the SNR – Signal-2-Noise Ratio of the endless set of errors/warnings from the tool. So much so that we have heard of customers giving up on linters, primarily those freebies/bundled with simulator ones. While it is true that some of the reported ones are indeed serious issues, the ROI (Return On Investment) of having RTL designers navigating through the ocean of messages is too little in many cases.

OTOH there are clear set of issues that a good LINTer can spot for you quite easily, for instance see:

Sledgehammer to crack a nut? – Use right tools for right class of design errors/bugs: 

Essentially it comes to the art of “Finding the needles in the haystack” and in a timely manner:


Don’t loose your heart, there is a silver lining with modern day linters/static analysis tools. We TeamCVC covered the rise of new age linters back in 2010; Recently Ascent from RealIntent showed the below case study that proves this very point:


In the following table you will see the results of the analysis of Ascent IIV on 130K gates of RTL logic that was done by NEC in Japan.

Table 1.  Ascent IIV Intent Checks and Failures Report for a 130K Gate Block.
The tool generated 31,186 intent checks that were analyzed by its various engines and 2,999 failures were produced in total.  The hierarchical reporting of the tool characterized these failures into several categories.  It determined that by fixing the Primary Errors (purple column in the table) this would eliminate the duplicate, secondary and many structural errors.  In this benchmark, 181 primary errors were identified.  This represents a dramatic contraction of almost 95% of the total failures from the tool.  You can read further comments by NEC here.

So next time when you hear of the Linter’s SNR issue, do recollect this “smart categorization” and push for it in your solution or move/upgrade to better ones. you should however check on local support team for such new age products though as these tools do require some hand-holding especially in the initial stages of adoption.

Good Luck,


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SystemVerilog-VMM to UVM migration – first step

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation:


A small VMM-built-in utility class is provided as part of VMM named vmm_version. It has few interesting methods, First one being:


The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. For instance when VMM was first released in opensource TeamCVC made it working on all EDA tools, fixing any Synopsys specific features in the VMM base class code. Then we donated it back to the community and other vendors did more changes. If you are interested in running it with Aldec’s Riviera-PRO feel free to contact us or directly

The other function that prints more information along with the “configurations  used to generate the VMM base code” is:     vmm_ver1

A sample output of the above from Aldec’s tool is below:


So in case you are migrating from VMM (or OVM) to UVM, call us for hints, case studies, or even better join our workshop on this topic.



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Invitation to contribute to next generation Verification standard – join the eWG

To all the ASIC Verification enthusiasts interested in pushing the limits beyond existing languages and methodologies, here is your chance to contribute and be part of the change. As many would be aware, IEEE 1647 standard defines Functional Verification language e.

For over a decade e language has provided many advanced features for verification engineers that have recently been adopted to other languages such as SystemVerilog as well. The most recent one being “soft constraints” – see:  And as more customers demand more features, the working group on e language has been busy adding new proposals. In our last group meeting we agreed on having four working sub-groups.

These are:-
1)      Temporal Working Group
2)      Messaging Working Group
3)      Types and Operators Working Group
4)      General Working Group
So this is a general request/invitation for group leaders and for other members of the group to help drive them on. Each group will be responsible for going through the donated documentation for each new/modified feature, and for getting it into a state where it can be integrated into the standard, which will be done in conjunction with the editor. Working Groups can meet independently of the main group, reporting progress back or discussing issues where necessary.

So get started with your innovation beyond your current job/employer and grab the chance to influence wider community. Join us @ eWG:



Co-chair, IEEE 1647 Working group

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SystemVerilog UVM comparer – hidden gem in show_max

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/uvm_sequence_item. However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as:


Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:


Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc.

Now, when we simulate this with Aldec’s Riviera-PRO here is what we see:


But now the user asked 2 good questions:

  • How does it know what to compare?
  • Why is printing only 1 mismatch and not all?

The answer to the first question above is the `uvm_field_int macro. In the transaction model one should add:


The UVM_ALL_ON flag in the macro instructs the code to consider each field for all built-in routines/methods like copy/clone/compare etc. We also suggest adding the post_randomize for ease of debug.

Now moving onto the 2nd question that the user asked: “Why does it print only 1 mismatch”?” – the built-in uvm_comparer has a field show_max that controls how many mismatches to show/display and its default value is 1. One could change it and set it to its maximum using SystemVerilog’s bit-fill operator ‘1. Now when we pass the modified comparator object to the compare() routine we will see al mismatches:


Sample output from Riviera-PRO is below:


Hope you find this hidden-gem nside uvm_comparator useful in your debug cycles. Have fund and contact us via in case you’ve a tough debug problem to crack.


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Quick start on ABV for VHDL designers – OVL + VHDL + Modelsim

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well folks at Mentor have been supporting OVL, VHDL etc.

As valuable QVP partner with Mentor, we at TeamCVC decided to make it easier for end users. When we dug further we did realize it is not out-of-the-box. Hence we created a quick start example and uploaded it to our website.

Feel free to grab it from here: 

It is certainly a quick example just to demo the flow. Will add more soon. Here is the README for the example:

CVC’s OVL VHDL Example with Modelsim

To compile and run OVL VHDL example in Questa/MTI follow this example

We’ve used ovl_one_hot on a DUMMY signal, just to demo the flow.

You need latest OVL 2.7 release. We’ve included a part of that in this tar ball

To run
cd run_dir
make ovl

Still we strongly suggest VHDL users to choose PSL. But in case you need OVL, this example could help. Feel free to grab it from here: 

Send us your comments via

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Making Verilog simulations a fun and useful game – welcome to EDAPlayground

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC

Ever wondered if you can run Verilog Sims from a Web Browser?

Well, playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground. EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free, and, since it is web-browser based, it runs on any OS. And you can be up and running in few minutes, without having to install EDA tools, licenses etc.

EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy — select the simulator on the option panel, and click Run.


If the sim creates a *.vcd wave dump, it is possible to view waves using EPWave browser-based viewer. To enable EPWave, simply set the following checkbox on the option panel:

Open EPWave after run

The wave window will open after the simulation completes.


EDA Playground has several code examples to play with, such as:

“Our short-term and international training attendees have always wanted a platform to run/play with simulations after the training sessions on their own, at their own schedule” says Mrs. Ajeetha Kumari, CEO of CVC Pvt Ltd. She continues “So far they had to install, manage their own tools or rely on their employers/universities to provide such a support; with the launch of EDA Playground this process can get simplified a lot in near future”.

To find out more about EDA Playground, watch the following video. Recommended viewing quality is 720p. EDAPlayground on You Tube

Victor Lyuboslavsky, Founder of Victor EDA

Technology partner, guest blogger at CVC