Here is the tale of Mr. Avit Kori, who recently finished his 2-month advanced Verification course @ CVC (www.cvcblr.com/trainings). He possessed strong design skills with Verilog/VHDL but was finding it hard to scale upto modern day VLSI job requirements before joining CVC. At CVC not only did he learn technologies such as
VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf
SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf
VMM: http://www.cvcblr.com/trng_profiles/CVC_DR_VMM_profile.pdf
He also contributed [...]
Archive of entries posted by admin
Creating quality Verification engineers for VLSI ecosystem
NextOp’s assertion synthesis and our recent FIFO experience
Based on DVCon 2010 paper on SystemVerilog Assertions – 2009 (see www.cvcblr.com –> Publications) we recently got our FIFO model run through NextOp’s BugScope tool. It produced some interesting stuff. The main one I liked is
pop |-> full;
This is an eye opener property – as this should never be the case! But BugScope indeed indicated [...]
Combine Lint & Formal equiv-checker
That could be a killer combination for specific functional verification goals. For instance look at recent SNPS’s webinar on MVRC & Formality @ http://bit.ly/9oupo9
Other ideas I have on using Formal equiv checker in functional verification are to automate Gate Level debug, debugging X’s, porting RTL TB’s to GLS etc. Need a good API + formal [...]
Welcome the next generation Verification Methodology – UVM
For all those System Verilog geeks, lovers, followers here is a sigh of BIG relief – at last we have a UNIVERSAL Verification Methodology that all the 3 major EDA vendors would openly support (and hopefully promote as well). As we speak, UVM-EA (Early Adaptor) release is now available. Take a look at it from [...]
SystemVerilog Q vs. assoc-array – which one to use for scoreboard
Hello,
Queues in SV provide more search related functions such as “find_first/find_index” etc. that aid in scoreboard modeling. It is true that assoc-arrays are slightly better at memory foot-print. Also indexing can be done via any field there, not in Q – but in Q one can use the “find_first..with” to do the same.
As you can [...]
SystemVerilog covergroup – bins and the value set matching
During our last week Verification with SystemVerilog class (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ), an interesting question popped up during functional coverage session. As user defined bins are created for vectors in SystemVerilog, what if the value set range is not divisible by the specified number of bins (say in a fixed number of bins case)?
Consider:
[cpp]
bit [4:0] vec_5bits;
covergroup [...]