They say “innovation never stops” – it is true for the SystemVerilog language committee. And it is very true for our co-author Ben Cohen, who even at the retired age keeps updating himself on latest on SV, VMM, OVM, UVM and of-course SVA. Ben Cohen is the Accellera nominated representative for the SV-AC committee on IEEE dev team.
See TOC at: http://systemverilog.us/SVA3rdE_preface_toc.pdf
The cover of this book is a NASA photograph of Mars, taken by Curiosity. Just like how Mars is enormously big, the verification state space of most of the modern day designs are extremely large. While there have been several advances in the area of "stimulus" or "activation of potential design errors", the amount of checking being done during such activation (either via simulation or formal analysis) demands detailed, precise design specification. This is precisely where SVA fits in the design flow. Just like how the whole world awaits pictures & findings from Curiosity to learn more about Mars, SVA could be used by the design verification teams to learn about the functional quality of designs.
Here is what the forewords say:
Dennis Brophy Director of Strategic Business Development, Mentor Graphics.
In 2010, research showed use of SystemVerilog was up more than 233% over prior years with more than 7
out of 10 design and verification engineers using it. Even more telling was the use of the SystemVerilog
Assertions (SVA) part of the standard. Research showed that assertions enjoyed the same high level of use
with 7 out of 10 design and verification engineers adopting SVA.
Assertion based verification (ABV) methodologies has been found to address design and verification
challenges and the market use reflects it. The assertions portion of the IEEE SystemVerilog standard has
also been enhanced over these years to extend and improve what can be done with them based on the
cumulative experiences of the design and verification community to date.
The third edition to the SystemVerilog Assertions Handbook comes at a time when the IEEE updates its
popular SystemVerilog standard and at a time when the FPGA community is increasing its adoption of
SystemVerilog assertions as well. Design and verification engineers will find the handbook useful not just
as a resource to begin to adopt assertions, but to apply the latest additions and updates found in the IEEE
standard to the ever pressing design and verification challenges.
Sven Beyer, Product Manager Design Verification, OneSpin Solutions
The SystemVerilog standard itself has been very much alive with two updates in 2009 and now in 2012, enhancing many existing features and
adding numerous new ones. So more and more engineers are exposed to SVA while at the
same time, the standard quickly evolves, trying to address the growing needs of those engineers for more
productivity. This definitely calls for a first class reference documentation – and this book, SystemVerilog
Assertions Handbook, 3rd Edition by Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa
Piper, provides such a comprehensive reference manual that is suited for both SVA power users and
novices. It introduces assertion methodologies and gives a clear idea on what assertions are good for,
addressing both coverage and the complementary strengths of dynamic and formal verification. It carefully
lays out the numerous SVA language constructs one by one in a way that really gets across to the typical
engineer, emphasizing the intended usage, adding telling examples, and listing the counter-intuitive pitfalls
that may cost an engineer precious time in debugging. Therefore, this book is sure to find its place on the
bookshelf of numerous engineers all over the world, and since it is the first comprehensive reference
manual to also address the IEEE 1800-2012 standard, for example with its numerous enhancements to the
checker construct, it is sure to remain on this shelf and be extensively used for quite some time.
Stuart Sutherland , SystemVerilog Training and Consulting Wizard
Sutherland HDL, Inc.
The complexity of the design we need to verify requires that an assertions language has a robust set of
features and capabilities. The SystemVerilog Assertions (SVA) language meets that rigorous requirement.
The robustness of SVA also means that it can be challenging to learn to use SVA — and to use it correctly.
The SystemVerilog Assertions Handbook is an essential resource for overcoming that challenge. The book
examines the use of SVA in the context of verifying true-to-life designs. Thorough explanations of each
feature of SVA show the where and how to use SVA correctly, as well as point out pitfalls to avoid. At my
company, we feel this book is so essential for understanding and properly using SVA, that we include a
copy of the book as part of the standard training materials in all of our “SystemVerilog Assertions for
Design and Verification Engineers” training workshops.
Cristian Amitroaie CEO, Amiq
The first benefit this book brings is a systematic and clearly organized perspective on SVA, from planning
to terminology, from how assertions work and how to debug them, to coverage driven and formal
verification using assertions. This includes the language clearly identified rules, and many tables and
figures annotated with comments.
Second it offers many concrete examples. Examples are fresh air for engineers when diving into complex
topics and this book has plenty, including the mapping between natural language and the corresponding
Third, it contains guidelines on what to use and what to avoid, based on experience with both SVA and
UVM. Knowing and following best practices are essential to engineers these days, when work pressure
doesn’t leave much time to carefully digest all the implications of the highly sophisticated means we use on
a daily basis.
This is a book every engineer should keep handy!