Job code: DVL-08-01

Exp: 4-8 years

Note: there are also individual contributor roles. Summary of skills needed:

- Advanced verification methodologies, preferably SystemVerilog – including testbench development
- (G)DDR2/3 verification experience
- Good problem solving, teamwork

Send CV to career@cvcblr.com
———-

As an ASIC Verification engineer at high end semiconductor design house, verify the design and
implementation of the industry’s leading Graphics and Video
Processors. Specific areas include 2D and 3D graphics, mpeg, video,
audio, high-speed IO interfaces and bus protocols, and memory
subsystem design. In this position, you will be responsible for
verification of the ASIC design – architecture and micro-architecture
- and it may include pre-silicon, emulation, and post-silicon
activities. You are expected to understand the design and
implementation, define the verification scope, develop the
verification infrastructure and verify the correctness of the design.
You will be working with architects, designers, pre and post silicon
verification teams to accomplish your tasks.

Requirements:
Exposure to design and verification tools (VCS or equivalent
simulation tools, debug tools like Debussy)
Good debugging and problem solving skills. Scripting knowledge
Expertise in SystemVerilog or similar HVL
C/C++ programming language experience desirable
Experience in architecting test bench environments for unit and system
level verification
Experience in verification using random stimulus along with functional
coverage and assertion-based verification methodologies
Good communication skills and ability & desire to work as a team
player are a must
Qualification:
BS / MS with 8+ years of experience

VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf

SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf

VMM: http://www.cvcblr.com/trng_profiles/CVC_DR_VMM_profile.pdf

He also contributed to our OVM inhouse project creating quality code, testplan etc. It is that project experience that provided true differentiator in excelling and getting the right breakthrough!

We, TeamCVC wish him all the very best in his future endeavors.  Here is what Avit had to say about our TeamCVC:

Hi Team CVC,

Today I am very pleased to inform you that I got an opportunity to join Perfectus Technology as a Verification Engineer.

My sincerest thanks to the Team CVC for training and guiding me. I am really proud that I got the opportunity to be trained under Srini sir and Ajeetha mam. Again Anand, Prabu and Jijo always looked forward to solve my doubts. Without all of this I would never have been able to achieve the level of confidence required to become a good verification engineer.

I really appreciate all your efforts for giving me have such a memorable experience at CVC.

Thanks and Regards.

Avit Kori

http://in.linkedin.com/pub/avit-kori/1b/6/ba3

Playing around debugging some complex assertions in Qeusta? Here are some tips:

1. Use vsim –assertdebug

2. Add –novopt for trivial code containing assertions + stim alone as otherwise many signals get optimized away. On real designs, perhaps you are better off with +acc* (Read doc for more)

3. Once the GUI comes up, the assertions are not listed in its own browser – ideally I would have liked to see a menu item under “Tools” menu. But it is hidden under “View –> Coverage –> Assertions” – GOK why! (GOK – God Only Knows)

4. Before starting simulation, enable ATV

5. After sim one can do “view ATV” for advanced debug!

That’s “advanced OVM” for this week!

Enjoy OVMing..

TeamCVC

www.cvcblr.com/blog

Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that this is the first time ever I look at this design/env as the original author moved out of the company (sign of good times ?) and am given to fix the code ASAP – in next 15 minutes that’s (sounds way too familiar, Huh?).

# Number of fware xactn 19
# ** Fatal: [Time 0 ns] Test cfg Solver failure
#    Time: 0 ns  Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../
rt_test_03.sv Line: 83
# ** Note: Data structure takes 9699728 bytes of memory
#          Process time 0.03 seconds
#          $finish    : ../test/san_rt_test_03.sv(83)
#    Time: 0 ns  Iteration: 2  Instance: /san_rt_top/san_rt_test_pgm_0

So what next? Consult our friendly Questa SolveDebug: add vsim –solvedebug and bang you go…

It does 2 things:

1. It prints the minimal set of conflicting constraints,
2. Creates a stand-alone test to reproduce the failure in a crisp testcase. See below:

Minimal set of constraints from user-code

# ../test/san_rt_test_03.sv(82): randomize() failed due to conflicts between the following constraints:
#     ../test/san_rt_test_03.sv(59): san_rt_test_cfg_0.cst_reasonable_fw_xactns_1 { (san_rt_test_cfg_0.no_of_fware_xactions > 32′h00001360); }
#     ../src/san_rt_fware_gen.sv(42): san_rt_test_cfg_0.cst_reasonable_fw_xactns { (san_rt_test_cfg_0.no_of_fware_xactions < 32′h00000032); }
# ** Fatal: [Time 0 ns] Test cfg Solver failure
#    Time: 0 ns  Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../test/san_rt_test_03.sv Line: 83
# ** Note: Data structure takes 9699728 bytes of memory
#          Process time 0.02 seconds
#          $finish    : ../test/san_rt_test_03.sv(83

Testcase being created by Questa (system verilog code, can be run standalone)

# ../test/san_rt_test_03.sv(82): randomize() failed; generating simplified testcase scenario…
# —– begin testcase —–
# module top;
#
# class TFoo;
#     rand bit [15:0] \san_rt_test_cfg_0.no_of_fware_xactions ;
#     constraint all_constraints {
#         // ../src/san_rt_fware_gen.sv(42): san_rt_test_cfg_0.cst_reasonable_fw_xactns { (san_rt_test_cfg_0.no_of_fware_xactions < 32′h00000032); }
#         (\san_rt_test_cfg_0.no_of_fware_xactions  < 32′h00000032);
#         // ../test/san_rt_test_03.sv(62): san_rt_test_cfg_0.small_tst_cst { (san_rt_test_cfg_0.no_of_fware_xactions < 32′h000013ec); }
#         (\san_rt_test_cfg_0.no_of_fware_xactions  < 32′h000013ec);
#         // ../test/san_rt_test_03.sv(59): san_rt_test_cfg_0.cst_reasonable_fw_xactns_1 { (san_rt_test_cfg_0.no_of_fware_xactions > 32′h00001360); }
#         (\san_rt_test_cfg_0.no_of_fware_xactions  > 32′h00001360);
#     }
# endclass
#
# TFoo f = new;
# int status;
#
# initial begin
#     status = f.randomize();
#     $display(status);
# end
#
# endmodule
# —– end testcase —–
#

Now that was easy to fix, simply override the test-specific constraint in the inherited test_cfg than “adding to it”. Glad I met my deadline for today!

Hats off Questa – wish it prints the vsim –solvefaildebug automatically on such failures to log file.

TeamCVC

www.cvcblr.com/blog

Jijo PS, Thirumalai Prabhu, Kumar Shivam, Avit Kori, Praveen & Nikhil – TeamCVC www.cvcblr.com

2010 has been a great year so far for us the verification community in India – with constant news of fresh hirings, new project starts etc. For us at CVC things have been as busy as we would like them to be – both from trainings and consulting perspective. Now that we have an army of VMM-aware engineers, we decided to let them see how the different product companies leverage on the matured methodology during SNUG India 2010, earlier this week. The results were amazing – every one of the attendees thanked us for letting them feel the vibrant VMM straight from the horse’s mouth – the real users, developers etc. Here is a quick collection of various VMM updates from SNUG India 2010 – as seen by TeamCVC. Expect to hear more on VMM1.2 soon from us as now I have a young team all charged up with VMM 1.2 (thanks to Amit @SNPS).

WRED Verification with VMM

In her paper on “WRED verification with VMM”, Puja shared her usage of advanced VMM capabilities for a challenging verification task. Specifically she touched upon:

· VMM Multi-Stream Scenario gen

· VMM Datastream Scoreboard with its powerful “with_loss” predictor engine

· VMM RAL to access direct & indirect RAMs & registers

What we really liked is to see real application of some of these advanced VMM features – we were taught all of these during our regular CVC trainings and we even tried many of them on our own designs. It feels great to hear form peers on similar usage and to appreciate the value we derive out of VMM @CVC and the vibrant ecosystem that CVC creates around the same.

As they say, a well stated problem is half-a-solution. In this case the presenter did a great start by correlating Bangalore’s erratic traffic pattern to that of a “congested network”. Alas VMM can’t really solve road traffic woes, maybe just yet, anyone want to give it a try?

System-Level verification with VMM

Ashok Chandran, of Analog Devices presented their use of specialized VMM components in a system-level verification project. As a junior engineer, I often wondered where exactly will we seek the help of specialized VMM base classes like vmm_broadcast and vmm_scheduler

At the end the audience learnt what are some of the unique challenges a SoC verification project can present. Even more interesting was the fact that the ever growing VMM seems to have solution for a wide variety of such problems, well thought-out upfront – Kudos to the VMM developers!

Ashok also briefed on his team’s usage of relatively new features in VMM such as vmm_record and vmm_playback and how it helps us to quickly replay streams. At times VMM seems to have too many features, especially for juniors, but it is this kind of exposure that we get during SNUG that opens up our eyes to a wider world of reality!

On the tool side, a significant learning for me (Jijo) was the usage of separate compile option in VCS, am sure to add in my future work.

VMM 1.2 for VMM users

Amit from SNPS gave a very useful and upto-the-point update on VMM 1.2 for long time VMM users. When we learnt VMM at CVC and started developing VMM-envs, we always felt more automation is feasible. Infact we had an intern project on writing scripts for the same (such as the start_xactor for instance). It was rejuvenating to listen to the VMM 1.2 run_tests feature and the implicit phasing techniques. Though look like little “magic” these features are bound to improve our productivity as there are lesser things to code-debug and move-on..

Amit also touched upon the use of TLM 2.0 ports and how they can be nicely used for integrating functional coverage, instead of using the vmm_callbacks. With due credits to the power of callbacks – as a junior I always longed for a simpler means to integrate functional coverage – and here comes my savior J

The hierarchical component creation and configurations in VMM 1.2 puts us on track for the emerging UVM and is very pleasing to see how the industry keeps moving to more-n-more automation and makes us realize that Verification is a HOT topic and is bound to be so for years to come. Glad to be Verification Engineer J

A truly vibrant ecosystem enabled by CVC -VMM Catalyst member

A significant addition to this year’s SNUG India was the DCE – Designer Community Expo – a genuine initiative by Synopsys to bring in partners to serve the larger customer base better all under one roof. CVC (www.cvcblr.com) being the most active VMM catalyst member in this region was invited to setup a booth showcasing its offerings. As noted in another blog on CVC (www.cvcblr.com/blog) it was a near stampede response in our booth as we gave away several books including our popular VMM adoption book http://systemverilog.us/?p=14 and all the new SVA Handbook 2^nd edition http://systemverilog.us/?p=16 .

Here is a snapshot of CVC’s booth with our VMM and other offerings.

released ISA-Frost & Sullivan 2009-11 India Semiconductor Market Update. Here are excerpts from his speech during this release:

To face tomorrow, the Indian semiconductor industry has to rise to meet the challenges from other Asian countries and aid in developing the ecosystem.

China and Vietnam are emerging as strong competitors in this industry. The Indian industry will have to address certain vital links in its ecosystem,

such as systems engineering, venture capital and IP protection, to become more robust.

It will also have to take measures to build up a skilled and technically trained, design-aware workforce for the future.

CVC is well poised to address this very challenge – both in terms of creating the workforce and delivering top-notch services

to the industry. Look at our EIC: http://www.slideshare.net/svenka3/anubhuti-engineering-incubation-centre-eic 

And all our other trainings focused on experienced folks at www.cvcblr.com/trainings

Not convinced yet? Give us a call +91-9620209226 or drop in at CVC @ HSR Layout, Bangalore, India, www.cvcblr.com/about_us see you here soon

More details at: http://www.uvmworld.org/blog/?p=115

TeamSpecman representatives for this Blog interview: Kishore Karnane, Adam Sherer, Hannes Froehlich, and Ariel Melchior

During recent ClubT India session I met the famous “TeamSpecman (www.twitter.com/teamspecman )” to see what’s new about Specman/e and general verification roadmap from them. To my pleasant surprise they offered much more than what I got to know from regular eWG updates (CVC is part of the eWG @ www.ieee1647.org to contribute & stay on top of the upcoming language updates therein). The Incisive team has joined hands with the Specman team to roll out the “Specman Advanced Option” for power users of verification. Now, just around DAC time, I got a chance to interview the “TeamSpecman” including some of their core R&D folks to delve a little deep into the motivation behind the updates, some of them being rolled out and others in pipeline. What resulted is the following interactive Q&A session, sit back and enjoy..and welcome to Advanced Specman!

TeamCVC: Hello Gentlemen, welcome to this interactive, Q&A blog – an innovative style of introducing some cool technologies. Having been pioneers in the field of verification ever since the early days of introducing constrained-random, coverage-driven verification to OVM-e multi-language era – you folks have been locked onto some of the toughest verification challenges. With so much focus on languages for verification, what do you have in store for the DV community up-next?

TeamSpecman: On the verification front, Cadence is introducing many new and enhanced technologies at DAC this year. For example,

· Cadence Incisive Specman Elite supports the world’s most advanced verification users with the unique aspect-oriented features of the e language. It has a new Specman Advanced Option available that adds advanced debug and performance features, including multi-core support.

· Cadence Incisive Enterprise Simulator (IES) has added support for the Universal Verification Methodology (UVM), the emerging Accellera standard, new low-power and debug features as well as an Incisive Advanced Option for multi-core performance.

· Cadence Incisive Enterprise Verifier (IEV) is a new verification desktop product with simulation, formal, and dual-engine modes. It includes all the simulation features of Incisive Enterprise Simulator and all the formal features of Incisive Formal Verifier.

· Cadence Incisive Enterprise Manager (IEM) enables automated verification planning, runs tools on a server farm, and collects metrics across these runs to judge verification completeness.

As part of the Cadence EDA360 vision, we will be discussing these technologies in much more detail at DAC this year. We encourage you to stop by the Cadence Booth 1334, Hall B from June 14^th – 16^th in Anaheim, CA

TeamCVC: Some of the most advanced DV teams across the globe have been using Specman for years with millions of lines of e-code in existence and they are looking for “more out-of-the-box” performance. More so, with the languages (e & SystemVerilog) for verification have been standardized, it is key to see how users can leverage on multi-language, multi-vendor/simulator environments. For instance with a typical code base of 25K+ lines of e-code, the performance of compiler is becoming a limiting factor in the overall productivity of the DV team.

The good news though is, on the compute infrastructure side, multi-core machines have become very affordable with 2, 4, 6 or even 8-core CPUs occupying every user’s desktops. How does one leverage on this in day-to-day DV tasks?

TeamSpecman: Srini, yes, this has been one of the most requested enhancements from our Specman/e customers. So, the good news is that the Specman Advanced Option does allow the customer to leverage the multi-core servers during the compilation mode. We have already seen significant performance improvements with this newly added functionality. We are seeing close to xN (N= # cores) speedup in compilation time. In other words, we have seen that the performance improvement very nicely scales linearly through 8 cores but then the shared memory management in the underlying CPU architecture causes sub linear scaling beyond 8 cores.

TeamCVC: So in short, my compiles can be as fast as that of number of cores on my server? That’s exciting as it can easily cut down our development cycles, debug cycles etc.

TeamSpecman: That is correct. We have been seeing linear scaling in performance. It is very exciting!!

TeamCVC: When one talks of compiled code, a pressing issue has been the debug or the lack of it, I must say. While we all love high performance simulations, the limited debug-ability of compiled code has been a constant source of pain. What are your plans on that front?

TeamSpecman: Srini, yes, debugging complied code can be a pain. That is why we have added another new functionality in the Specman Advanced Option. This new feature will enable e source line debug of compiled code. This will reduce the overhead of maintaining different flows for debug and regression runs. The customers will be able to just run in the compiled mode all the time and be able to set a breakpoint in their compiled code for easy debug. This functionality will be available in the Q4 timeframe. Overall, this can improve the overall performance up to 2x.

TeamCVC: WoW! So now I can set a BP (breakpoint) *anywhere* in my compiled e -code and do “step..step..step” from there on – am I hearing it correctly or am I day-dreaming here?

TeamSpecman: You are definitely hearing it correctly. This is no longer a dream. It will be a reality very soon in the Incisive 10.2 release. We are looking for some customers who would like to beta-test this functionality in their verification environment.

TeamCVC: Here is another common scenario – with complex designs like large processors, packet engines, the initialization/setup/boot sequence takes significant time. All tests are running through similar initial stage that can be saved and later on restored in order to trigger the ‘interesting’ scenarios , either by running different seed or by loading new test. How do you foresee this challenge to be addressed in wider context?

TeamSpecman: We address this limitation again in the Specman Advanced Option by enabling the customer to leverage the “restore” command that allows users to start a new random test from a saved state post simulation start. In other words, we will provide the ability to run until some point, save the state, start the test from the saved point using different seed or load another e test. This has been confirmed by customers that can enable them savings of over 60% productivity improvement

TeamCVC: This is a high-voltage feature for sure with potentially several takers hungrily waiting for it. Where can we find more information about this?

TeamSpecman: Yes, every time we present this functionality to a customer, their eyes light up since they can see the significant time savings with functionality. The gain heavily depends on the length of the bring-up time (reset) of the environment. The typical estimation is about 50-60% while there are customers that have estimated it even higher. So, as you can see, instead of tweaking the simulator to squeeze another 5 – 10% performance improvement, “e” is going to leapfrog over the currently available HDL simulator performance. Again, we would love to find customers who are interested in beta testing this functionality too. This functionality will be available in the Incisive 10.2 release. We would recommend that customers contact their local Cadence Sales Representative to get more details.

TeamCVC: Given all these “advanced” capabilities, tell me something – am I Cadence-limited to avail these benefits or can I still use another HDL simulator with Specman for the testbench part?

TeamSpecman: That’s the beauty of this new option. It works with either use model. The customer can use Specman as part of the Incisive Enterprise Simulator (IES-XL) or they can use it as a standalone product with a 3^rd party simulator. So, this new option will work with VCS and Questa simulators too. In other words, customers will not be Cadence-limited.

TeamCVC: What are your thoughts on extending these capabilities to SystemVerilog based solution as well?

TeamSpecman: We at Cadence are committed to supporting all standards for our customers. Given the vast user base of matured and advanced verification users in Specman, it makes perfect sense for us to invest heavily in Specman/e. Infact it serves as the perfect platform for us to introduce, test-drive some of these advanced capabilities with Specman – simply because there is a large base of existing e-code that demand such power. Once we get enough feedback and the technology with other languages advance to where e is today, we are committed to make them available there too – at the end of the day the customers have their way and we at Cadence are committed to making our customers successful.

TeamCVC: So, to summarize things – as a long term Specman user put it during ClubT Bangalore, “Specman made industry realize functional verification as an engineering discipline on its own”. Having pioneered verification for over a decade, it is time for them to go beyond just the language and IPs and enable users to be more productive! Thanks gentlemen for your time and more importantly YOU – the readers having gotten so far. Feel free to add your comments right here @ www.cvcblr.com/blog or if you are at DAC, stop by the Cadence Booth 1334, Hall B from June 14^th – 16^th.

BTW, CVC’s flagship -course is out and is called “EssentialE” – targeted at beginners with an advanced eVC level course being in the works. Checkout www.cvcblr.com/trainings for updates!

NextOP

One of the most promising start-ups in the assertion based verification domain. They have been in stealth mode for a few years. Only recently quite a bit of information has been let out about their technology. It all started with an eval report from a real user and active follow-ups from then – see: http://www.cvcblr.com/blog/?p=147

Ben Cohen (www.systemverilog.us) recently had some good discussions about this technology based on our DVCon-2010 paper on SVA paper (contact us to get a copy: http://www.cvcblr.com/about_us) It did find some interesting bug via simulation run –> property extraction –> coverage hole –> bug! It is a little long route, but however it is an interesting approach. See details at:http://www.cvcblr.com/blog/?p=163

Make sure you visit their booth @DAC (NextOp exhibits at Booth #1442) to learn more. In a nutshell their technology is about analyzing existing RTL & testbench+testcase (via regression) and extract quality properties for your design – then it is upto the RTL designers to qualify whether these “properties” are assertions/coverage/don’t cares. Their promise is minimal noise, but your mileage may vary!

Vennsa’s OnPoint

If you ask anyone in EDA/Semiconductor industry about the “elephant in the room” problem in front-end VLSI, the answer is loud-n-clear DEBUG! Besides SpringSoft/Novas noone seemed to have the perseverance needed to sail through tough times trying to address that problem. (Remember Veritools, anyone BTW?) Now we have a genuine attempt to automate the debug – Vennsa’s OnPoint. Not much is known yet about it, but here is a picture (Copyright by Vennsa http://www.vennsa.com/ ):

This actually fits very nicely with our Unique workshop on “Debug” (see: www.cvcblr.com/trainings) – wherein we look at some of the common debug problems and demonstrate how little tricks with TCL, GUI/Markers etc. can save you hours if not days!

Look at some of our earlier Tweet’s  on OnPoint at www.twitter.com/sricvc to get some more info.

I’m sure we will hear more about it in coming weeks/months.

Jasper’s ActiveDesign

One of the most charismatic EDA tools that I’ve come across with so far – that’s if they really deliver on being the “Twitter of RTL Design” expectation that has been set of this. A picture is worth more than…here you go:

Read more about it at: http://www.cvcblr.com/blog/?p=144

Zocalo-tech

Do you care to approach your ABV adoption more methodically? Quoting Harry Foster, all time ABV promoter: (from his invited tutorial entited: “Assertion-Based Verification: Industry Myths to Realities”,

……”what differentiates a successful team from an unsuccessful team is process and adoption of new verification methods. Unsuccessful teams tend to approach development in an ad hoc fashion, while successful teams employ a more mature level of methodology that is systematic”. ……

Now Zocalo is one vendor trying to address that “methodology” aspect of ABV – via their Bird-dog primarily. We looked at their Zazz-OVL and even during today’s SVA training locally (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we were discussing how complex some of the OVL choices could be and I mentioned ZazzOVL – as the Dutch puts it, it is “jammer” (pronounce it as “yammer”, see: http://forum.wordreference.com/showthread.php?t=359560) that we didn’t have the tool handy to show off the value (during the lab session I mean). So make no mistake – their ZazzOVL is very very handy indeed – if you are adding OVLs that’s.

Coming back to their offerings – Bird-dog is a very interesting approach, very much for those assertion enthusiasts who look for “where is the maximum ROI of adding assertions”. Their Visual-SVA is like a “temporal GUI/editor” for complex SVA coding, not my personal cup-of-tea, but I do see value for some there. However generating “traces” for assertions within Visual-SVA is certainly a good attempt. Let’s see how they fair in real life usage! Visit Zocalo Tech Booth # 1509

The all new UVM (a la erstwhile OVM)

Sure you have heard of that – UVM, a sincere effort from Accellera to arrive at a “Universal” methodology from those seemingly competing OVM & VMM. Unless you want to risk your company not paying off your DAC bills, you wouldn’t want to miss that UVM booth Honestly – I believe every one is looking forward to that. As the Accellera PR puts it:

Accellera’s DAC breakfast, sponsored by Cadence, Mentor and Synopsys, will feature a standards update with an overview of how the Universal Verification Methodology (UVM) standard supports verification tool interoperability and gives IP and EDA users more choices, and a panel on “UVM: Charting the New Territory.” This event continues the celebration of Accellera’s 10 years of standards excellence.

For the first time, all 3 major vendors “sponsor” one event promoting ONE methodology – a great news indeed for the users. BTW, there is Aldec catching up on the SystemVerilog support with Riviera-Pro product line. Ask them for VMM/OVM/UVM support updates at: http://www.aldec.com/registration/dac

Agnisys’s OVM/UVM management kits

A young EDA company based in Noida, India with solid EDA background (Anupam). They have iDesignSpec & iVerifySpec as products – one is for Register automation and another for overall Verification management. The REG automation has been a long awaited/wished for stuff, almost 8 years back we at Intel used Perl+DOC (Table) for something similar – glad to see a much more finished end product now. It can emit VMM-RAL, OVM and soon perhaps the UVM code too.

Sapient-Inc’s IC management

Another  young EDA company, according to the founder – Subash, a long time chip designer/manager:

I started Sapient-IC from the pain and frustration of managing IC products. The die size grows, schedule slips, VP yells at everybody. This is what I want address. Analytics for decision makers, comparative analysis for design choices to financial analysis.

Breker’s Trek

A not-so-young EDA company (compared to the likes of NextOp/Zocalo etc.) with some interesting success stories with NVidia, STMicro. Their Trek is certainly a refreshing approach to testcase writing – especially for SoC Verification. See: http://www.cvcblr.com/blog/?p=148 for more details.

RealIntent’s Ascent

So much has been told, written about Linters – yet its adoption has been hampered heavily by the amount of “noise” it creates. Realintent’s Ascent claims to be less on that – and that is their primary seeling point. Not sure how they achieve that – given the natural side-effect of trying “find faults” with any given code.

SpringSoft

Check with them what’s up with their Certess/Certitude – it is an innovative approach for sure – mutation based TB qualification. As much as we have heard locally, there have been success and also some additional “noise”.