Being a “Pedantic Engineer” – self check for fresh VLSI engineers

As a sub-thread of a core technical discussion, Alan Fitch from UK brought up an important question: See the full thread (more technical @: http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&p=16440#16440 

Alan Fitch writes:

I agree with your answer, but as a pedantic engineer (is there any other sort?) 

I really wish there isn’t any other – but not sure if many young engineers agree with that. BTW I do consider myself young, am really talking about fresh/beginners/early career folks. I see some degradation on that side, I was at KCG Tech (http://www.kcgcollege.com/) this weekend for their NCV09 conference. We from CVC were  delivering our VoW tutorial series on "Functional Verification methodology", and also a case study on Assertion-Based Verification by Thirumalaiprabhu, my colleague @CVC. I met with the teaching staff there. Had a long chat on this very topic – the fresh graduates recently aren’t pedantic – atleast in VLSI domain. The reasons the staff attribute are:

  1. Too much use of cellphones
  2. Time wasted on Social Networking sites (Orkut, FB etc.)

 

To me – if you are an engineer – no matter which field it is, you *MUST* be pedantic – else you are not set for a complete, satisfying career – you may earn more money than many of us, may fly across oceans etc. But completeness is beyond all these – one’s self satisfaction about what we do everyday in professional life!

 

Signing off!