As you all may know by now, IEEE 1800-2009 was recently approved. There were many updates in SystemVerilog core, the Assertions, and the addition of the checker, a new type of entity where several assertions and verification code can be defined just like a module/interface. In addition the checker can be inlined [...]
Archive of entries posted on November 2009
Training on “Protocol Verification using SystemVerilog Assertions”
December is usually the time of holidays, relatively work load etc. Given the challenging job scenario this is also the best time to hone your skills and face the New Year with new skills, explore new job avenues, segments etc.
CVC is announcing a week long certificate course on standard protocol verification. At the end of [...]
Make best use of your Dec holidays: Verification Fest (VFest)
December is usually the time of holidays, relatively work load etc. Given the challenging job scenario this is also the best time to hone your skills and face the New Year with new skills, explore new job avenues, segments etc.
CVC is launching its highly successful 2 weeks certificate course on Functional Verification using SystemVerilog with [...]
ASIC Design Verification for FPGA designers
…Step upto ASIC world with SystemVerilog, Assertions & Testbench
CVC (www.
Technorati Tags: trainings
cvcblr.com) is announcing a new session of its 10-day course on “FPGA-2-ASIC_DV-with SystemVerilog” – a step-by-step approach to introduce modern day Design & Verification challenges & solutions for FPGA designers. It is structured as follows:
Basic Session
Comprehensive Functional Verification (CFV)
SystemVerilog basics (SVB)
Advanced Session
ABV Introduction
SystemVerilog Assertions [...]
CFV + SystemVerilog basics
Title: CFV + SystemVerilog basicsLocation: www.cvcblr.comLink out: Click hereDescription: SystemVerilog basics.
Look at SVB portion from this profile:
http://www.cvcblr.com/trng_profiles/CVC_VSV_WK_profile.pdf
This is intended mainly for FPGA designers, so the focus will be building fundamentals than building complex OOP testbench.Start Date: 2009-12-8End Date: 2009-12-9
Verification Using SystemVerilog (VSV)
Title: Verification Using SystemVerilog (VSV)Location: www.cvcblr.comLink out: Click hereDescription: Our popular corporate training on SystemVerilog for Verification. Details at:
http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdfStart Date: 2009-12-5End Date: 2009-12-7
Comprehensive Functional Verification (CFV)
Title: Comprehensive Functional Verification (CFV)Location: www.cvcblr.comLink out: Click hereDescription: See contents, agenda at: http://www.cvcblr.com/trng_profiles/CVC_IN_CFV_profile.pdf
Mainly for new comers, FPGA designersStart Date: 2009-12-4End Date: 2009-12-8
Advanced VHDL for Verification
Title: Advanced VHDL for VerificationLocation: www.cvcblr.comLink out: Click hereDescription: Advanced VHDL techniques for Functional Verification. For a close-door customer, not a public class. Start Date: 2009-12-2End Date: 2009-12-3
Verilog HDL
Title: Verilog HDLLocation: www.cvcblr.comLink out: Click hereDescription: Basic Verilog HDLStart Date: 2009-11-25End Date: 2009-11-26
SystemVerilog tip: watch out enum and randc
Recently an interesting question was raised by SystemVerilog user on randc usage with enum. To illustrate, consider the following code:
[cpp]
typedef enum {red, green, blue, yellow, white} house_color_type;
class c;
randc house_color_type enum_0;
[/cpp]
Spot anything wrong above? Perhaps not? As it goes with randc an implementation needs to remember all values generated so far before recycling! So it [...]