VerificationOnWeb (VoW)

Assertion Based Verification has certainly been one of the mostly debated topics over the last half-a-decade. So much so that one of the past DVCons was full of SystemVerilog & PSL papers on ABV that someone commented it is “ABV conference” than DVCon (was it DVCon 2005?2006?)
Even then the adoption rate has been slower [...]

For those of us who have been following the EDA marketing over several years, it is no surprise that there are dedicated marketing professionals within big EDA companies focussing on conveying message/confusing the ecosystem if needed (unfortunately). We have several anecdotes starting from “VHDL is dead” back in 2003 (http://www.eetimes.eu/uk/17408257) and guess what, last month [...]

Good news for all those Emacs + SystemVerilog users. Puneet has just now released his SV Snippet for Emacs, see:
http://coverification.org/2009/12/17/systemverilog-snippets-for-emacs/
Will certainly try it out ASAP. Good start Puneet, keep it up. Thanks for sharing it!

Interesting analysis of how Verification effort is being spent across industry:
http://tinyurl.com/dbg-it-man
(See the pie-chart, Figure 2). It goes very much inline with what we have been hearing from customers, competitors and also from our own own experience. So DEBUG is THE area if one were to automate within Functional Verification. I’m little surprised to see [...]

 
In case you missed it: http://chipdesignmag.com/display.php?articleId=3723
I mentioned this during our recent Advanced VHDL TB class during PSL session and attendees were very interested. Today I got a mail back from Chandramohan asking for the link, sent to him and read it once again (must admit, not in full indepth PCI-e level). Overall an excellent paper, [...]

OpenSource VMM 1.2 is finally out, see vmmcentral.org – we have been mentioning it to many of our training attendees as “it is coming, it is coming”..now it is HERE!!
 
One of the greatest challenges we face is when our previous SystemVerilog/VMM attendees attend our newer classes (for upgrade, learn other methodology etc.) – they [...]

Recently @VGuild Mike asked”
 
Does anyone use ModelSim’s FLI for verification? What are the pros and cons of this? I’ve been considering adopting SystemVerilog for writing test environments (we code our designs in VHDL and use PSL for assertions and functional coverage) but, from what I can gather, [...]

Another piece partly covered in Cooley’s report, but for those interested in full details (more technical updates coming in soon)..
Here are my (and my team, who is looking at it closely during an eval) observations on Breker’s Trek tool. What we really like about this tool is that it an add-on to any existing methodology/environment [...]

Some of you might have seen our report of DAC from John Cooley. Here is our full version of NuSym report for those interested. Trek to follow (wiht more updates after the DAC report was sent out)..
We at CVC have been tracking Nusym’s technology for a while. I visited their booth & demo and here [...]

While there is so much talk about ABV in the market, the adoption is still far less than desired/expected by the buzz! Harry Foster from Mentor tries to find some rationale in his new blog at:
http://blogs.mentor.com/verificationhorizons/blog/2009/12/06/abv-and-people-from-missouri/#comment-6
 
Here is what we from CVC feel about it (also added as comments in that blog).
>> What are the obstacles [...]