In our regular SystemVerilog, VMM trainings (www.cvcblr.com/trainings) we demonstrate the power of callbacks to go beyond the obvious usage – specifically a case study to demonstrate transaction level debug. While this topic has been around for very long time (IIRC, Cadence/DAI first provided it via SignalScan), its real application in day-to-day debug has not been [...]
Archive of entries posted on February 2010
Potential research areas on ABV – for a Masters thesis
As part of our BUDS internship program (http://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf) we work with some of the leading edge educational institutions in India (and one in the USA, BTW). One of our current inters is working on Assertions Based Verification using OVL. In less than a month he has picked up so much so that he says he [...]
Why CVC’s trainings are so special
As in any business, there are always lead players and those who try to “mimic” them. We see our trainings also the same way – let’s admit there are few players in this game in our region. However what sets us apart from the rest? Few:
1. First of all we serve the whole industry at [...]
Debug SystemVerilog code the right way with Verdi
Srinivasan Venkataramanan, CVC Pvt. Ltd. www.cvcblr.com
Sreenath V, CVC Pvt. Ltd. www.cvcblr.com
One of the many challenges in taking over a block developed by others is the quick ability to grasp the big picture fast and then delve deep into some focus areas. Talking of SystemVerilog based Verification code base (say with a base class [...]
Early validation of RTL – with no Testbench!
Srinivasan Venkataramanan, CVC Pvt. Ltd.
Looks like Jasper DA (www.jasper-da.com) is on a mission to drive simulation a passé J On a more serious note, their recently announced ActiveDesign (TM) technology sounds pretty interesting for early RTL validation. Before I hear that “Aha..that’s my favourite LINTing”, hold on.. this is much more than that – one [...]
Signs of maturity in EDA tool built-in examples
During a recent look at ActiveDesign product from Jasper (http://www.jasper-da.com/products/ActiveDesign.htm), I was pleasantly surprised to see a high quality design being used as the case study. Usually such early product demos contain tightly canned examples, showing only the relevant tool features and much less on the actual design. Here is a refresher – we get [...]
SystemVerilog covergroup – bins and the value set matching
During our last week Verification with SystemVerilog class (VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ), an interesting question popped up during functional coverage session. As user defined bins are created for vectors in SystemVerilog, what if the value set range is not divisible by the specified number of bins (say in a fixed number of bins case)?
Consider:
[cpp]
bit [4:0] vec_5bits;
covergroup [...]
Debug SystemVerilog macros with VCS-DVE
Srinivasan Venkataramanan, CVC Pvt. Ltd.
Rashmi Talanki, Sasken
John Paul Hirudayasamy, Synopsys
An extract from a little lengthier post @ http://www.vmmcentral.org/vmartialarts/?p=922 – focus here only on Debug side on this post:
One of the powerful features of SystemVerilog is the ability to create TEXT macros (those `define s) with arguments – they can create fairly complex code in [...]