Based on DVCon 2010 paper on SystemVerilog Assertions – 2009 (see www.cvcblr.com –> Publications) we recently got our FIFO model run through NextOp’s BugScope tool. It produced some interesting stuff. The main one I liked is
pop |-> full;
This is an eye opener property – as this should never be the case! But BugScope indeed indicated [...]
Archive of entries posted on May 2010
NextOp’s assertion synthesis and our recent FIFO experience
Combine Lint & Formal equiv-checker
That could be a killer combination for specific functional verification goals. For instance look at recent SNPS’s webinar on MVRC & Formality @ http://bit.ly/9oupo9
Other ideas I have on using Formal equiv checker in functional verification are to automate Gate Level debug, debugging X’s, porting RTL TB’s to GLS etc. Need a good API + formal [...]
Welcome the next generation Verification Methodology – UVM
For all those System Verilog geeks, lovers, followers here is a sigh of BIG relief – at last we have a UNIVERSAL Verification Methodology that all the 3 major EDA vendors would openly support (and hopefully promote as well). As we speak, UVM-EA (Early Adaptor) release is now available. Take a look at it from [...]
SystemVerilog Q vs. assoc-array – which one to use for scoreboard
Hello,
Queues in SV provide more search related functions such as “find_first/find_index” etc. that aid in scoreboard modeling. It is true that assoc-arrays are slightly better at memory foot-print. Also indexing can be done via any field there, not in Q – but in Q one can use the “find_first..with” to do the same.
As you can [...]