Playing around debugging some complex assertions in Qeusta? Here are some tips:
1. Use vsim –assertdebug
2. Add –novopt for trivial code containing assertions + stim alone as otherwise many signals get optimized away. On real designs, perhaps you are better off with +acc* (Read doc for more)
3. Once the GUI comes up, the assertions are not [...]
Archive of entries posted on July 2010
Fun with Assertion Debugger in Questa – few tips
SystemVerilog OVM’s apply_config_settings – why & were?
Arayik Babayan, a friend of mine from Armenia asked me what is the use of “apply_config_settings” in OVM. As you may be aware SystemVerilog is a flexible language that can be used for building highly configurable and scalable verification environments. OVM adds a great deal of capabilities on top of plain “system verilog” to make [...]