Increased user momentum at CDNLive India

Quick summary of what I liked at recent CDNLive India. Read live tweets @

First of all, the venue is FRESH – ITC Royal Gardenia hotel, a welcome change from regular Leela/Taj :-) Second, the first few sessions were JAM-packed with more than 25 customers standing (with all seats occupied). This was surprising as the audience beta the Bangalore traffic to be there at around 9.30 AM.

On the technical front, well let’s focus on what we know best – Front-end Design & Verification. Frankly – I was not alone who got totally confused about which “Verification” track to choose from. There was this

  • “FED + Verification track”
  • System Design & Verification track

I first though it was the FED that I should be in, as it contained one of my much awaited Nokia paper on Formal/ABV/IFV usage. But my good friend @CDN Maruthi Srinivas helped with clarification. His explanation:

First of all sorry for confusion, this year we had so many good papers on Verification and we had to fit as many as we can. We decided to move some of the Formal/ABV papers to FED track. The core Verification papers are on the Track-V

Now being @ the common session, John Bruggeman did an excellent job with his EDA360 talk. With so much being tweeted about it, honestly I got little saturated prior to his talk. But his talk truly rejuvenated the topic and his expressive demo revealed the vision well inside 3 slides. Kudos JohnB!

Next to see was TomAnderson’s Verification roadmap – strangely this was presented at Track-IV/FED. Luckily I was there in that track and as ever before, Cadence’s vision was great – especially linking the Conformal LP and Functional Verification/MDV is very thought provoking. The “Advanced Specman” was known to us at CVC, but for many it was new there. And with similar capabilities being explored for SystemVerilog in the roadmap, there was enough for everyone to cheer about!

On the technical papers – a noted aspect that almost every attendee shared is – the quality and depth of these papers this time around was amazing. Be it the DFT Verif paper from TI (90 % of DFT logic bugs were caught by IFV flow), the TLM-e paper from ST-Micro and/or the Arch Model Verif with Specman by TI.

I personally enjoyed the Freescale paper on “Corner Case analysis with Formal”, to avoid repeating it, read more about it at: 

Nokia’s Modem IP Verif paper was one of the best presented ones IMHO and Manish Goel did an excellent & upto-the point job of staying on target. There were enough audience questions in his session than many others and even another presenter from TI (He got the best paper award, didn’t get his name though) shared some of his views during those interactive discussions. This I felt was true “customer-2-customer” interaction happening live before a full room audience – something that the CDNLive team can be very happy about.

One of the best audience Q was raised during an Assertion paper (guess the TI one):

  • “While IFV sounds great, user still needs to write those white-box assertions, is there any automation available”?

Though the presenter didn’t use this specific feature, the CDN rep/AE was quick to note that indeed IFV has the ability to extract certain classes of properties from RTL.

..and for those looking for more quality assertions, explore the partner technology of BugScope from NextOp:

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