Working with default arguments in SystemVerilog & OVM hierarchy building

Recently Amit (Yet another successful VLSI engineer from CVC’s incubation, asked this:

In OVM/UVM ( I am little confused about the way components are hooked-up hierarchically. Consider the code below:


In the above constructor ,sometimes I am writing parent =null and some times only parent ,and then passing in;, blindly i am doing this ,but i am not understanding why i am making parent=null and sometime leaving this as parent . what will be the effect of making so. kindly help me.


As an enhancement to Verilog, System Verilog allows “default values” for function/task (methods) arguments. By doing so it allows the caller of these methods to have the flexibility in number of arguments – a.k.a variable arguments to a function (though not overloading as in VHDL). So in the example above, the new has 2 arguments, both having default values.

If we had: (NOTE: the 2nd argument has NO default value)



then the caller of this function must pass atleast 1 argument.


Summary: if a default value is provided in the function declaration, then while calling the function, that argument becomes “optional”.

Now what is the impact of this in OVM context? Actually quite a bit – it is about the “TB hierarchy” – a.k.a print_topology in OVM/UVM. See few screenshots from Aldec’s Riviera-Pro ( 2011.02 version below:

Consider a simple OVM based env with:

env –> agent –> monitor

If monitor is constructed with “parent” set to “this” (i.e. the agent), then we get:




If monitor is constructed with “parent” set to “null” then we get:




It gets little murkier with OVM’s factory playing an interim layer with create – but that’s left as an exercise for the readers :-)

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