Real number randomization in SystemVerilog

 

Folks working on AMS (Analog & Mixed Signal) Design-Verification often require real numbers for things like Signal-to-Noise-Ratio (SNR). With so much buzz around SystemVerilog and its clear strengths on Constrained Random Verification support, engineers wonder how they could leverage it for “real randomization”.

Unfortunately SystemVerilog doesn’t directly support “rand real” declaration (weird reasons given by EDA developers, while a google on “random float number” reveals quite a few hits). However recall that SystemVerilog is built on top of Verilog and Verilog has some beautiful twin-functions for real <—> bits:

 

$bitstoreal

$realtobits

Here is a neat trick to use them for a signal-to-noise ratio random generation (Problem originally reported at: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4413)

 

Notes:

1. We have used new SystemVerilog 2009 syntax for “extern” constraint – nice one indeed to be in line with extern tasks/functions.

2. Also the %p –> Very handy one indeed

3. Used the post_randomize() for one of its best use models – display what got generated automatically. We teach this in our VSV training (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) and every customer appreciates that use-case for post_randomize.

 

Picture1

 

In case you want to learn SystemVerilog and jump onto this bandwagon before it is too late, join our training seesions – weekdays, part-time or weekend, see: http://www.cvcblr.com/trainings for details.

 

Enjoy SystemVerilog & AMS

TeamCVC

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