If you have been in the ASIC/FPGA industry for the past 5 years or so, it is highly unlikely that you haven’t heard of these buzz words:
- ABV – Assertion Based Verification
- CRV – Constrained Random Verification
- CDV – Coverage Driven Verification
While many ASIC teams have started using these in mainstream, FPGA users are still catching up with theses. One of the primary reasons has been that many FPGA designers use VHDL for RTL and Testench traditionally. (Though there are some high end Verilog users too, let’s talk about them in a separate blog. Meanwhile those folks can see how to adopt System Verilog for FPGAs from: http://slidesha.re/KtLlFu )
While these modern verification technologies are language independent, there is an impression in the industry that they are provided only via SystemVerilog and is thus restricted for Verilog/SV users. Some VHDL RTL teams have been forced to migrate to SystemVerilog just for this purpose – frankly speaking, a die-hard VHDL fan wouldn’t like it and also for teams using VHDL for long it is way too hard to do this migration in short timeframe. More important question is – do I need to migrate to adopt these technologies? – The answer is technically NO. VHDL has been very strong in “adaptability” to various requirements and stood strong amidst tough competition. Its rich features such as overloading, encapsulation (via packages), configurations, data structures etc. have been exploited by various applications such as: modeling, RTL design, testbenches etc.
Assertion Based Verification in VHDL
Recently temporal assertions capability has been added to native VHDL from IEEE 1850-PSL and hence the new VHDL 2009 standard has full fledged temporal expressiveness natively. See a PSL tutorial @ http://www.project-veripage.com/psl_tutorial_1.php
Constrained Random Verification
Given the complexity of designs being done using VHDL and FPGAs it is becoming increasingly difficult to rely just on directed stimulus. Constrained random generation allows exploring newer paths in every simulation run.
VHDL with its package capability allows building constrained random generation feature natively into the language without much hassle. Recently released OS-VMM infact provides it off-the-shelf. See: http://osvvm.org/archives/category/randomization
Coverage Driven Verification
Coverage as a metric to measure verification progress has been around for decades in verification. Code coverage has been widely used by RTL teams. Recently Assertions via PSL-VHDL provide temporal coverage and can be very handy to capture functional coverage of control oriented features. For data oriented features, coverpoint, cross etc. can be created in VHDL via packages. And OS-VMM does exactly that for all VHDL users. See: http://osvvm.org/archives/339
In summary – all the modern verification technologies are now available to VHDL users natively – without any additional cost (of a mixed language simulator for instance). The OS-VVM is a great starting point for coverage & constraints and PSL-VHDL provides all the temporal capabilities. Start doing better verification in VHDL with: http://www.osvvm.org