In one of the semiconductor conferences, Dr. Satya Gupta http://bit.ly/KlQpxr mentioned on a lighter note that the Semiconductor/VLSI needs to be promoted more among young Indian engineers and need to be made more “attractive”. (Guess it was Mentor’s U-2-U in 2010, anyone?) – few of the panelists and audience threw out ideas on how to do the same – via contests, TV shows etc. Taking it little more seriously and using social media we at CVC (www.cvcblr.com) believe our blogs/tweets & Facebook updates are doing exactly that.
Here is a “fairy tale” on how SystemVerilog MDAs work (or not work) with UVM field macros. Consider that we have a 3-D array (2 unpacked dimensions and 1 packed dimension) as shown below (“mda_3d” in s2p_xactn below):
While it sounds simple enough, the devil lies in “detail”. When you need to copy/clone/compare you need to ensure this mda_3d is included just like other fields. Huh? That’s what UVM supports via “field_macros” isn’t it? How about:
Oh my dear! Hold your breadth – this works for scalar types, and for 1-D arrays but NOT beyond . Since System Verilog supports “arbitrary” dimensions in MDAs (Multi-Dimensional Arrays), the UVM base class doesn’t provide macros beyond 1-D arrays. Bummer, so what’s next? Here is your helpline – the uvm_object::do_copy.
Here is a simple code snippet that augments the built-in automated “copy” routine to include user defined MDA such as our “mda_3d”.
With that – UVM has once again proven that while it is not obvious why it has so many hidden “gems” – they are all useful on a case-to-case basis. In Hindi we say “Har eak cheez zaroori hota hai”. As the popular AirTel advertisement goes (India specific, for International readers, see: AirTel commercial ad). In case you can related your facebook friends to UVM “features/functions/base classes” and wonder “How come I have so many friends” – as the ad says “Every friend is useful”