Invitation to contribute to next generation Verification standard – join the eWG

To all the ASIC Verification enthusiasts interested in pushing the limits beyond existing languages and methodologies, here is your chance to contribute and be part of the change. As many would be aware, IEEE 1647 standard defines Functional Verification language e.

For over a decade e language has provided many advanced features for verification engineers that have recently been adopted to other languages such as SystemVerilog as well. The most recent one being “soft constraints” – see: http://www.cvcblr.com/blog/?p=629  And as more customers demand more features, the working group on e language has been busy adding new proposals. In our last group meeting we agreed on having four working sub-groups.

http://www.eda.org/twiki/bin/view.cgi/P1647/Meeting78Minutes

These are:-
1)      Temporal Working Group
2)      Messaging Working Group
3)      Types and Operators Working Group
4)      General Working Group
So this is a general request/invitation for group leaders and for other members of the group to help drive them on. Each group will be responsible for going through the donated documentation for each new/modified feature, and for getting it into a state where it can be integrated into the standard, which will be done in conjunction with the editor. Working Groups can meet independently of the main group, reporting progress back or discussing issues where necessary.

So get started with your innovation beyond your current job/employer and grab the chance to influence wider community. Join us @ eWG: http://www.eda.org/twiki/bin/view.cgi/P1647/

Regards

Srini,

Co-chair, IEEE 1647 Working group

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