Rejuvenating VLSI Design Verification

CVC strongly believes that knowledge grows when shared! Our commitment to the semiconductor industry is deep rooted. Our books, tutorials, papers and code downloads stand as strong testimonial to our commitment.

We also have a very active blog at www.cvcblr.com/blog

Come and share your thoughts, we work across geographies, timezones - so feel free to contact us via info@cvcblr.com if you would like to blog with us here!

Below is a growing list of our publications and models. Drop us an email info@cvcblr.com with specific title (of paper, model) that you are interested, we will be glad to send it across to you.

Papers, tutorials, Models!

Tutorials: 

• Functional Verification Primer, NCV09
• Advanced Functional Verification using modern methodologies, NCV09
• SystemVerilog Assertions - Case study, includes SVA-2009 constructs. 
• SystemVerilog tutorial and Cross Point fabric Verification - case study, VoW Jun 09, at Mentor Grahpics Hyderabad
• PSL tutorial originally published @ Project VeriPage, download it from here.
•  "Pragmatic Adoption of Verification Methodology Manual (VMM) for Re-usable Transaction-Based Testbenches in SystemVerilog" - Tutorial in DVCon 2007

Models:

• Visualizing AVL Tree in simulation via SystemVerilog-DPI 
• VMM Scheduler code
• SVA Run time variable Delay code
• VHDL Probe package - Hierarchical references in VHDL, simulator independent TB code
• SystemVerilog Assertions book code
• VMM Book code
• PSL Book code
• Printing timescale in multi-million hierarchical Verilog design - VPI application

Papers: 

• DVScrutiny and revamp of a derivative Digital Image Processing ASIC, presented at SVUG Bangalore 2009!
• HW-FW co-simulation using SystemVerilog TestBench, Brocade & CVC. SNUG India 2009

• Ying-Yang of VLSI eco-system in India. Keynote speech at ISCO-09 

• Affirmative Design Verification of a Digital Still Camera (DSC) using SystemVerilog – a case study. Accepted for ASQED-09

• Achieveing higher quality designs with SystemVerilog & Questa, published in Verification Horizons, DVCon 09 edition

• “Image processing DSP Verification using SystemVerilog + VMM” in SNUG India 2007. 
• “Leveraging traditional TB while adopting modern Verification technologies" - CDN Live! 2007
• VMMing a  SystemVerilog Testbench by Example- SNUG SanJose 2006. This paper received  “Technical Committee Award”.
• “Understanding the key elements of a VMM based testbench” in Verification Avenue October 2006.

Our books!

SystemVerilog Assertions Handbook 1st Edition

Pragmatic Approach to VMM Adoption

Using PSL/Sugar 2nd Edition