VLSI- Design Verification
CONTENTS
1. VLSI- Design and Verification
We are a 17 year old world-famous organization with high technology quotient. We’ve trained more than 10,000 engineers world-wide and have enabled 1000+ fresh engineering graduates to realize their dream VLSI career.
VLSI Design Verification Engineering (DVE) is an exciting field with tremendous opportunities for fresh graduate with right skills. We at CVC have been at the helm of DVE since 2004. If you are a fresh engineering graduate or a junior
engineer looking to make it big in VLSI domain, look no further.
2. Class Details:
- Duration: 6 months of full-time course
- Prerequisites: BE/ME, Btech/Mtec- ECE, EEE
- Enrolling for a class: Please refer to Registration section.
3. Trainers Profiles
A. Srinivasan Venkataramanan, CTO
http://www.linkedin.com/in/svenka3
- Over 20+ years of experience in VLSI Design & Verification
- Designed, verified and lead several multi-million ASICs in image processing, networking and communication domain
- Worked at Philips, Intel, and Synopsysin various capacities. Co-authored leading books in the Verification domain.
- Presented papers, tutorials in various conferences, publications and avenues.
- Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification
- Holds M.Tech in VLSI Design from prestigious IIT, Delhi.
B. Ajeetha Kumari, CEO AND MD
http://www.linkedin.com/in/ajeetha
- Has 18+ years of experience in Verification
- Implemented, architected several verification environments for block & subsystems
- Co-authored leading books in the Verification domain.
- Presented papers, tutorials in various conferences, publications and avenues.
- Has worked with all leading edge simulators and formal verification (Model Checking)tools.
- Conducted workshops and trainings on PSL, SVA, SV, OVM, E, ABV, CDV and OOP for Verification
- Holds M.S.E.E. from prestigious IIT, Madras.
4. Why CVC?
| Factor Vendor | CVC | XYZ training company | EDA Vendor |
| Training Delivery | World renowned experts | Part timers, in bet’n job engineers | Tool support Engineer |
| Focus | Verification | Language | EDA tools |
| Topics covered | User/Verification perspective |
Language perspective | Based on the tools strength |
| How Recently Updated | Last week | Months Back | As old as language was standardized |
| Verification Expertise | Yes | Depends on the trainer | No |
| Can I run labs across tools | Yes | Yes | No |
| Is Content Tool independent | Yes | No/Yes (Typically only one tool) | No |
| Global Footprint | Yes | No | Yes |
| Publications | Yes | No | No |
| Post training support | Yes | No | No |
| Online Technical Evaluation | Yes | No | No |
| Customization | Yes | No | No |
| Online Blogs | Yes | No | No |
| Extended Hands on | Yes | No | No |
| Code review | Yes | No | No |
| Architecture Review | Yes | No | No |
| Productivity Tools | Yes | No | No |
| Cost | Low | <Unknown> | Expensive |
5. Our Global Foot print
6. Other Relevant Courses
- SystemVerilog
- UVM Level 1(Basic)
- UVM Level 2(Intermediate)
- UVM Level 3(Expert)
- UVM RAL
- Art of Debugging with UVM
- ABV-UVM
- Go2UVM
- Graph Based Verification
- Formal Verification
7. Customer set(sub-set)
8. Salient Take-aways
SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple enhancements to existing constructs, addition of new language constructs
to the inclusion of a complete Object- Oriented Programming features. There are also considerable improvements in the usability of Verilog for RTL design.
8. Course Content
9.Registration
- Name, Email, Contact number of all attendees
- A coordinator name (In case of multiple attendees)
- Training module you are looking for
- Onsite or at CVC premises
- Tentative schedule – month & week (Indicate when your team is available to attend the training)