Rejuvenating VLSI Design Verification

DVAudit - is our executable, push-button Design Verification Auditing solution aimed at providing valuable means to improve your existing Design-Verification setup. It works on any existing Verification environments, identifies potential areas of improvement, common pitfalls and recommends solutions, all as an add-on solution to existing design-flow.

It is the culmination of more than 50 design-verification manual auditing experiences being converted into an executable form.

This is still very much work-in-progress, so stay tuned for updates!

Starting a new Design-Verification project? Looking for a solid starting point, taking into consideration your project requirements, constraints? Our Design-Verification Creator solution is the right tool-set for you to get started the fastest!

Leveraging on more than 20 man-years of experience in creating verification environments, we at CVC have captured these skills into a unique, cross-platform toolset to assist our customers in the fastest manner.

Our DVCreate caters to wide range of Design-Verification styles ranging from various requirements such as:

• Assembly, C based
• HDL (Verilog, VHDL) based
• HVL (IEEE-1647 - E, OpenVera)
• HDVL - SystemVerilog
• SystemC
• C++
• TCL/Perl/Python

Our early release is expected in the first quarter of 2010, so stay tuned for early release news!

The most obvious product line from a small Design-Verification company is that of IPs and we are no differnt! But we do the same DIFFERENTLY as we have first hand experience in the practical challenges in deploying various available IPs in the market. Our approach to IP development is different! We produce:

• Design IPs (DIPs) - synthesizable, RTL/Gate Level IPs
• Monitor IPs (MIPs) - Assertion based IPs to monitor standard protocols (SVA & PSL)
• Coverage IPs (CIPs) - Functional Coverage IPs to measure completeness of your verification effort - regardless of the DV environment you use
• Comprehensive Verification IPs (CVIPs) - with stimulus generator, BFMs, MIPs, CIPs all built-in

While it may look more of "packaging" at the first read, based on our vast experience of deploying existing solutions we have realized that no one-size fits-all. Most of the existing solutions require substantial change in existing customer flows. We at CVC rather take a pragmatic approach to IP development and deployment as our MIPs and CIPs can fit into any existing flows and start showing value as early as in Day-1 of deployment!

We also work differently on titles we choose to develop - we work on those with high ROI to begin with and leapfrog towards a larger armory of the same.

With modern day FPGAs such as Virtex-6 offering immense capacity and incredible speeds, it is changing the mindset of every ASIC design team who have traditionally been averse to FPGA prototyping as a viable means to validate during pre-silicon phase. With more and more complexity being added to ASICs, it becomes extremely critical to do just faster validation and only-software based simulations do not scale up for such requirements.

We at CVC have been doing FPGA prototyping for select customers and are now putting that experience in creating common platforms based on high-end FPGAs for sizeable blocks/sub-systems to be prototyped at incredibly affordable cost! We also work with our partners in creating testboards as required.