Rejuvenating VLSI Design Verification

We offer variety of Design-and-Verification services ranging from architecture to closure to review process. As it is a well known market segment we rather leave the descriptions unsaid, and state the names and expansions below:

• DVArch - Design-Verification Architecture development, selecting the right language for the porject etc.
• DVAuthroing - Implementing BFMs, stimulus generators, monitors, checkers coverage models etc.
• DVClosure - Closing the coverage, debug and test loop to arrive at safe silicon
• DVReview - Our UNIQUE offering to analyze the past Design-Verification project to leverage on key BKMs, learn from mistakes and idenitfy areas to innovate & improve. It is from this UNIQUE service that we have rolled out an innovative product named DVAudit.

As can be seen from the above list, our value addition to a project can occur at anytime regardless of which stage you are in your product cycle. So contact us to see how we can add value to your path to rirsk-free silicon via our value added services!

With design complexities steadily growing, the amount of verification to be done grows at much larger ratio. Thankfully innovation in FPGA domain has made it possible to handle large blocks, sub-systems and even complete SoCs on single/multiple FPGAs. Such prototyping solutions offer a complementary benefit to Pre-Silicon validation efforts by running stress tests, performance tests etc. without the heavy cost of full fledged emulation solutions.

Traditional ASIC houses have not budgeted for a separate FPGA validation activity and with tight economy prevailing, it is hard to create one of your own. CVC's FPGA Prototyping services fill exactly this hole and provide our customers an extended arm to perform key verificaton tasks at much larger speeds and capacities than what any software-only solution can offer.

Modern day EDA tools are really platforms than being point tools, they support multiple technologies, multiple languages and multiple interfaces. Typical EDA developer and tester is best confined to his/her own domain with no clue of the big picture.

On the other hand, the real users demand the most stable, well tested products and are wary of being "guniea pigs".

With vast Design-Verification background CVC offers the ideal bridge among these two seemingly divided worlds to make both ends successful. We offer services in the domain of:

• Language testing (LRM compliance)
• Methodology adoption
• Release qualification
• Migration experiments, leading to prioritized set of features needed in next major release of the tool
• GUI testing
• Performance testing

CVC has a very successful track record in assisting various EDA vendors. We have demonstrated, proven track record in:

• SystemVerilog compilers, simulators
• PSL
• Model checkers
• VHDl-Verilog mixed simulations
• Linting tools
• FPGA flow tools
• ESL tools

So if you are an EDA developer and want to test waters before customers find issues in your next major release contact us immedietly!

With our CEO & CTO having co-authored 4 books and numerous articles, tutorials etc. Technical writing is at the heart of CVC. Be it your next new feature document or your legacy design to be documented, our team of well versed technical writers can help you achieve your goals at affordable cost.