Category Archives: SystemVerilog

SystemVerilog Soft constraints usage in `uvm_do_with macro

Recently we were asked a good & interesting question:

  • How do I use “soft constraint” in the macro `uvm_do_with? What would be the syntax?

I say this is a good & interesting b’cos of 2 things:

1. The SV LRM doesn’t give an explicit example for this (it is fine, not that it should, LRM is not a textbook)

2. The use case should be considered (This specific user had a good need – for automatic coverage closure – or ACC).

Now quickly jumping to solution, based on our SystemVerilog 2012 tutorial that our CEO Ajeetha delivered at IIT Mumbai earlier in 2014 (http://on.fb.me/1yfcBSx), here is a code snippet:

image

For those who need a quick background on what are soft constraints, see: http://www.cvcblr.com/blog/?p=629 

Now with 3 major EDA vendors supporting this syntax, you should leverage on this more!

Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at: http://goo.gl/oq4FmF

Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:

  bit [7:0] msb_vec, lsb_vec;

msb_vec[7] = lsb_vec[0];
msb_vec[6] = lsb_vec[1];

// …

While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:

  msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic

But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator:

$display (” msb_vec: %b reverse: %b”, msb_vec, { << {msb_vec} } );

If the array was unppacked, there is a built-in array.reverse() available.

One of the good things about the modern, social media is we all stay connected atleast virtually – no matter where our careers take us to. In this case he is currently at Ahmedabad, Gujarat, India. So do feel free to contact us via info@cvcblr.com for any SystemVerilog related help!

Test Specification Language – the past, present and the future

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: http://www.goo.gl/BKuNEd ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of “how verification shall be effectively carried out”, the next level of “What defines my verification space” has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will look at most (if not all, and maybe more) of the predecessors to define the future language for “Test Specification”.

1. Mentor’s inFact has a graph based language (http://www.mentor.com/products/fv/infact/) and a nice GUI around it.

clip_image002clip_image004

2. Breker Trek (www.brekersystems.com) – one of the first EDA companies to promote Graph based verification. Breker strongly advocates use of Graphs for stimulus-coverage-checking – all 3 in one “scenario model”. To keep things true and open to our readers, CVC has been an official representative for Breker in India for few years by now.

clip_image006

3. Vayavya labs (http://vayavyalabs.com/technology/socx-verifier/) has a SOCX-Specifier that captures the scenarios and spits out SystemVerilog classes (a la UVM).

clip_image008

4. Cadence’s vPlan (extension to e) http://www.cadence.com/Community/tags/vManager/default.aspx – one of the earliest solutions in this space, has been in production use for many years at customer projects. Basically captures the plan-2-test-2-results flow in a XL form and/or vPlan file (ASCII) format. Allows teams to collaborate in a geographically distributed team by providing a common dashboard of the verification status.

clip_image010

5. SNPS VMMPlanner – http://news.synopsys.com/index.php?s=20295&item=122582 It also has a proprietary extension to SV known as HVP – Hierarchical Verification Plan.

clip_image012

6. CVC’s Assertion Driven Test Synthesis (www.cvcblr.com). As part of CVC’s Verification consulting engagements, we use an internal, time-tested approach to define the scenarios in an extended SVA-like syntax. The “test intent” is captured via SVA-like syntax and then our services team converts that to tests+checkers+scoreboard+coverage as per customer need on their chosen language & methodology. Contact srini <> cvcblr.com for more. 

7. Bluespec’s BSV www.bluespec.com – not really a test specification language, rather a rule-based specification language built on top of SystemVerilog syntax. Not sure if they eye this new language development as a good opportunity to donate their language, but we at CVC believe this will be a good anecdote to learn from.

8. SV’s own randsequence – a less known, less powerful feature of SystemVerilog called “randsequence” supports BNF style productions to specify the test-flow. Not very popular, though a detailed look by the proposed committee is worth, as we feel.

Maybe there are few more solutions around that we haven’t captured here, please do send the details to me via email (srini<>cvcblr.com), we will consider adding them here soon.

Now to conclude/wrap-up this (long) post, here are some abbreviations for this next generation language – surely a lot more names can be considered, a starting list:

. TSL – Test Specification Language

. VSL – Verification Space/Specification Language

. GSL – Graph/Goal Specification Language

SystemVerilog-VMM to UVM migration – first step

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation:

vmm_rpro

A small VMM-built-in utility class is provided as part of VMM named vmm_version. It has few interesting methods, First one being:

vmm_ver2  

The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. For instance when VMM was first released in opensource TeamCVC made it working on all EDA tools, fixing any Synopsys specific features in the VMM base class code. Then we donated it back to the community and other vendors did more changes. If you are interested in running it with Aldec’s Riviera-PRO feel free to contact us or directly www.aldec.com

The other function that prints more information along with the “configurations  used to generate the VMM base code” is:     vmm_ver1

A sample output of the above from Aldec’s tool is below:

vmm_ver3

So in case you are migrating from VMM (or OVM) to UVM, call us for hints, case studies, or even better join our workshop on this topic.

Regards

TeamCVC

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SystemVerilog UVM comparer – hidden gem in show_max

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/uvm_sequence_item. However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as:

uc1

Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:

 uc7

Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc.

Now, when we simulate this with Aldec’s Riviera-PRO here is what we see:

uc3

But now the user asked 2 good questions:

  • How does it know what to compare?
  • Why is printing only 1 mismatch and not all?

The answer to the first question above is the `uvm_field_int macro. In the transaction model one should add:

uc5

The UVM_ALL_ON flag in the macro instructs the code to consider each field for all built-in routines/methods like copy/clone/compare etc. We also suggest adding the post_randomize for ease of debug.

Now moving onto the 2nd question that the user asked: “Why does it print only 1 mismatch”?” – the built-in uvm_comparer has a field show_max that controls how many mismatches to show/display and its default value is 1. One could change it and set it to its maximum using SystemVerilog’s bit-fill operator ‘1. Now when we pass the modified comparator object to the compare() routine we will see al mismatches:

uc2

Sample output from Riviera-PRO is below:

uc8

Hope you find this hidden-gem nside uvm_comparator useful in your debug cycles. Have fund and contact us via info@cvcblr.com in case you’ve a tough debug problem to crack.

TeamCVC

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Asynchronous events and SVA – a quick primer

During our recent SystemVerilog Assertions update webinar (http://www.cvcblr.com/blog/?p=802) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.

sva_async

 

As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA.

So, if you’ve more challenging requirements, do drop in at CVC and we will assist you resolve them!

TeamCVC

Test your digital arithmetic – $urandom returns unsigned or signed?

SystemVerilog adds $urandom – a simple random number generator that returns a 32-bit UNSIGNED integer. Contrast it to good old $random – returns a 32-bit SIGNED integer.

Consider the below code snippet:

integer address;

initial begin : b1

  address = $urandom;

  $display (“%m address: %d”, address); end : b1

When you run the above code in Questa, one in a while you get:

# address = 90095195;

# address = -949724053;

First sight it looks strange, why is $urandom generating a negative number? Bug in the tool? Crazy? (See a real user post at: http://goo.gl/yp0WZ)

A bit of thinking, taking eyes away from monitor screen would help – follow your basics on digital arithmetic:

  • integer – a signed 32-bit number (in Verilog)
  • i.e. holds−2(n−1) through 2(n−1)−1. (2’s complement representation)
  • So if you assign even a 32-bit UNSIGNED number with the MSB set to 1 – it will be treated as “signed 31-bits”
  • Hence –> $urandom does generate 32-bit UNSIGNED, but when you assign it to a 32-bit signed integer, be ready for a surprise.

Not convinced yet? We at CVC like that attitude – be rebellious. Try the below code yourself. Notice we made address a 33-bit signed number, run it for yourself in a good simulator.

image

Send your comments via info@cvcblr.com for now (till we fix a hacker’s entry into our WP).

TeamCVC

OTG – On-The-Go SystemVerilog tip: Assoc arrays – allocate OTG

Sparse arrays in general (in many computer languages) exhibit ‘allocate-on-the-go” behavior. System Verilog is no exception. During today’s VSV training at CVC we had some interesting discussion on this topic. SV assoc-arrays get allocated on-the-go, while it is well known and talked about fact – it is clear for the “write” to array. What about “read”? For some early stage users it is not so obvious that a $display is a reader as well. Consider the following piece of code (full code later):

logic [7:0] logic_aa [int];

initial

  logic_aa[20] = 121;onthego

In the above code the 21st location gets allocated OTG, clear.

What about the following?

logic [7:0] logic_aa [int];

initial

  $display (“%m CVC: read AA: “, logic_aa[20] );

What would you expect? Error? Or allocate OTG? Hold your answer, let’s see full code:

aa_1 onthego

Any guess? Well, the $display on an un-allocated assoc-array element is a reader too, hence gets allocated OTG (On-The-Go), default value gets assigned. Isn’t that somewhat “not so good”? Well, that’s why a good tool like Questa (from Mentor) emits a warning in such case, see below:

aa_2

So next time when you use assoc-array ensure you recall this OTG behavior!

Safe journey with SV and CVC :-)

TeamCVC 

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Pinning down SystemVerilog program block

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother.

From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf).

Here comes a 2-minute run-down on this nice feature. Let’s look at some code:

 

PGM_1

Line 6: #10 DUT ‘reads” a signal named “sig_1”.

Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above)

Consider that the above “write” and “read” to the signal were done on “module” scope – this is potential “race” – as 2 different simulators can schedule these 2 initial blocks in arbitrary order. Such a race will be painful to debug, hard to migrate, harder to maintain etc. So how does bringing in program help here? Assuming you are familiar with System Verilog event scheduling mechanism (we cover this in detail during our SVA training – http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) one would recall that there is a region named “REACTIVE” region that executes AFTER the “design” region/assignments. The program block code executes in this reactive region thereby avoiding the races by language! One could visualize this by running the code above in any SV tool. Here is a snapshot with Mentor’s Questa 10.2:

PGM_2

 

As you can see in the log/transcript, the “DUT” gets done first and then comes the TB/program block – all in same time-stamp though.

Now that being guaranteed to be consistent across EDA tools, users have one-less thing to worry about in their Verification journey.

Do send your comments via training@cvcblr.com

Regards

TeamCVC

Raise a few eyebrows with SVA’s $rose

Assertions have always been our passion at CVC. The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late.

In one of our recent, part-time SVA training session (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions:

"Things look bright when SVA syntax is discussed. it gets better when we start discussions"

One of the nice features in SVA in the ability to detect rising edge with $rose. It is quite simple to understand when applied on single bit signal. For non-startes, it is simply a change from 0 to 1. That’s true for a single bit. What about vectors? In the below code, consider “addr” signal as 4-bit vector (logic [3:0] addr;)

If you thought it is 0 to 1 as in decimal, you are straightaway in for a surprise. If you suspect it is “bitwise” ORing of all bits – you are over-thinking on this. Consider the trace below along with SVA result (with Cadence’s IUS & nice Simvision GUI)

 

rose2

Consider an example of 4-bit vector  and few transitions.

rose6

That’s the change of LSB from 0 to 1 is really $rose.

Now consider the below transitions:

rose5

i.e. not every other bit counts here – only the change in LSB is considered. Did that raise an “eyebrow”?

Now consider an ascending order of “addr” values: (0 –>1 –> 2 -> 3 –> 4..)

image

Note that every alternate transition causes the $rose to be true, indicated by the “failed” notification in Simivision above – recall the system verilog assertion as:

$rose (addr) |-> 1’b0; // flag a failure, make it visible

Make no mistake, the $rose doesn’t work on “strictly ascending” consider few more traces below:

rose7

Now to raise few more eyebrows, consider the below trace with “descending” series of addr values:

image

So while a simplistic view of “0 to 1” is “ascending/increment”, the $rose is different when it is applied on a vector, even “descending/decrementing” transitions trigger $rose.

Now to summarize: $rose –> EVEN to ODD change :-)

Want to learn more SVA tricks, drop us a note via training@cvcblr.com to know about our next SVA training session in Bangalore.

Signing off,

TeamCVC