1. VLSI – Design Verification
2. Class Details
3. Trainers Profiles (Srinivasan Venkataramanan, CTO & Ajeetha Kumari, CEO and MD)
4. Why CVC?
5. Our Global Footprint
6. Other Relevant Courses
7. Customer Set (Sub-Set)
8. Salient Take-Aways
9. Course Content
10. Registration
We are a 17 year old world-famous organisation with high technology quotient. We’ve trained more than 10,000 engineers world-wide and have enabled 1000+ fresh engineering graduates to realise their dream VLSI career.
VLSI Design Verification Engineering (DVE) is an exciting field with tremendous opportunities for fresh graduate with right skills. We at CVC have been at the helm of DVE since 2004. If you are a fresh engineering graduate or a junior engineer looking to make it big in VLSI domain, look no further.
Duration: 6 Months of Full-Time Coursework
Prerequisites: BE/ME, B-Tech/M-Tech, ECE, EEE
Enrolling for a Class: Please refer to Registration Section
– Over 20+ years of experience in VLSI Design & Verification
– Designed, verified and lead several multi-million ASICs in image processing, networking and communication domain
– Worked at Philips, Intel, and Synopsysin various capacities. Co-authored leading books in the Verification domain
– Presented papers, tutorials in various conferences, publications and avenues
– Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification
– Holds M.Tech in VLSI Design from prestigious IIT, Delhi
– Has 18+ years of experience in Verification
– Implemented, architected several verification environments for block & subsystems
– Co-authored leading books in the Verification domain
– Presented papers, tutorials in various conferences, publications and avenues
– Has worked with all leading edge simulators and formal verification (Model Checking) tools
– Conducted workshops and trainings on PSL, SVA, SV, OVM, E, ABV, CDV and OOP for Verification
– Holds M.S.E.E. from prestigious IIT, Madras
Factor Vendor |
CVC |
XYZ training company |
EDA Vendor |
| Training Delivery | World renowned experts | Part timers, in bet’n job engineers | Tool support Engineer |
| Focus | Verification | Language | EDA tools |
| Topics covered | User/Verification perspective |
Language perspective | Based on the tools strength |
| How Recently Updated | Last week | Months Back | As old as language was standardised |
| Verification Expertise | Yes | Depends on the trainer | No |
| Can I run labs across tools | Yes | Yes | No |
| Is Content Tool independent | Yes | No/Yes (Typically only one tool) | No |
| Global Footprint | Yes | No | Yes |
| Publications | Yes | No | No |
| Post training support | Yes | No | No |
| Online Technical Evaluation | Yes | No | No |
| Customisation | Yes | No | No |
| Online Blogs | Yes | No | No |
| Extended Hands on | Yes | No | No |
| Code review | Yes | No | No |
| Architecture Review | Yes | No | No |
| Productivity Tools | Yes | No | No |
| Cost | Low | Unknown | Expensive |
– SystemVerilog
– UVM Level 1 (Basic)
– UVM Level 2 (Intermediate)
– UVM Level 3 (Expert)
– UVM RAL
– Art of Debugging with UVM
– ABV-UVM
– Go2UVM
– Graph Based Verification
– Formal Verification
SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis.
Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a complete Object-Oriented Programming feature. There are also considerable improvements in the usability of Verilog for RTL design.
Send us the following details:
– Name, Email, Contact number of all attendees
– A coordinator name (In case of multiple attendees)
– Training module you are looking for
– On-Site or at CVC premises
– Tentative Schedule – Month & Week (Indicate when your team is available to attend the training)
– You may email the details to training@cvcblr.com or fill in our contact form, or call us on +91-962 020 9223
