Category Archives: EDA

Test Specification Language – the past, present and the future

At DVCon-14, leading EDA vendor MENT has taken the initiative to propose a Test Specification Standard (see: ). Given that SV & UVM are well established and deep into their development, stability and adoption phase, the innovation has to come at next level of abstraction. Over the last decade, we at CVC have been working with customers (semiconductor design houses) and EDA partners in defining, evangelizing and deploying multitude of technologies and languages such as OVL, e/Specman, eRM, PSL, SVA, SV, VMM, OVM, AVM, UVM etc. While most of them address the key aspects of “how verification shall be effectively carried out”, the next level of “What defines my verification space” has been left for adjacent technologies. Now with this new initiative we are starting to see this problem being addressed. Here is a quick summary of various attempts that have been made to address this problem so far. Hopefully the new Accellera committee will look at most (if not all, and maybe more) of the predecessors to define the future language for “Test Specification”.

1. Mentor’s inFact has a graph based language ( and a nice GUI around it.


2. Breker Trek ( – one of the first EDA companies to promote Graph based verification. Breker strongly advocates use of Graphs for stimulus-coverage-checking – all 3 in one “scenario model”. To keep things true and open to our readers, CVC has been an official representative for Breker in India for few years by now.


3. Vayavya labs ( has a SOCX-Specifier that captures the scenarios and spits out SystemVerilog classes (a la UVM).


4. Cadence’s vPlan (extension to e) – one of the earliest solutions in this space, has been in production use for many years at customer projects. Basically captures the plan-2-test-2-results flow in a XL form and/or vPlan file (ASCII) format. Allows teams to collaborate in a geographically distributed team by providing a common dashboard of the verification status.


5. SNPS VMMPlanner – It also has a proprietary extension to SV known as HVP – Hierarchical Verification Plan.


6. CVC’s Assertion Driven Test Synthesis ( As part of CVC’s Verification consulting engagements, we use an internal, time-tested approach to define the scenarios in an extended SVA-like syntax. The “test intent” is captured via SVA-like syntax and then our services team converts that to tests+checkers+scoreboard+coverage as per customer need on their chosen language & methodology. Contact srini <> for more. 

7. Bluespec’s BSV – not really a test specification language, rather a rule-based specification language built on top of SystemVerilog syntax. Not sure if they eye this new language development as a good opportunity to donate their language, but we at CVC believe this will be a good anecdote to learn from.

8. SV’s own randsequence – a less known, less powerful feature of SystemVerilog called “randsequence” supports BNF style productions to specify the test-flow. Not very popular, though a detailed look by the proposed committee is worth, as we feel.

Maybe there are few more solutions around that we haven’t captured here, please do send the details to me via email (srini<>, we will consider adding them here soon.

Now to conclude/wrap-up this (long) post, here are some abbreviations for this next generation language – surely a lot more names can be considered, a starting list:

. TSL – Test Specification Language

. VSL – Verification Space/Specification Language

. GSL – Graph/Goal Specification Language

SystemVerilog-VMM to UVM migration – first step

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation:


A small VMM-built-in utility class is provided as part of VMM named vmm_version. It has few interesting methods, First one being:


The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. For instance when VMM was first released in opensource TeamCVC made it working on all EDA tools, fixing any Synopsys specific features in the VMM base class code. Then we donated it back to the community and other vendors did more changes. If you are interested in running it with Aldec’s Riviera-PRO feel free to contact us or directly

The other function that prints more information along with the “configurations  used to generate the VMM base code” is:     vmm_ver1

A sample output of the above from Aldec’s tool is below:


So in case you are migrating from VMM (or OVM) to UVM, call us for hints, case studies, or even better join our workshop on this topic.



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Invitation to contribute to next generation Verification standard – join the eWG

To all the ASIC Verification enthusiasts interested in pushing the limits beyond existing languages and methodologies, here is your chance to contribute and be part of the change. As many would be aware, IEEE 1647 standard defines Functional Verification language e.

For over a decade e language has provided many advanced features for verification engineers that have recently been adopted to other languages such as SystemVerilog as well. The most recent one being “soft constraints” – see:  And as more customers demand more features, the working group on e language has been busy adding new proposals. In our last group meeting we agreed on having four working sub-groups.

These are:-
1)      Temporal Working Group
2)      Messaging Working Group
3)      Types and Operators Working Group
4)      General Working Group
So this is a general request/invitation for group leaders and for other members of the group to help drive them on. Each group will be responsible for going through the donated documentation for each new/modified feature, and for getting it into a state where it can be integrated into the standard, which will be done in conjunction with the editor. Working Groups can meet independently of the main group, reporting progress back or discussing issues where necessary.

So get started with your innovation beyond your current job/employer and grab the chance to influence wider community. Join us @ eWG:



Co-chair, IEEE 1647 Working group

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SystemVerilog UVM comparer – hidden gem in show_max

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/uvm_sequence_item. However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as:


Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:


Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc.

Now, when we simulate this with Aldec’s Riviera-PRO here is what we see:


But now the user asked 2 good questions:

  • How does it know what to compare?
  • Why is printing only 1 mismatch and not all?

The answer to the first question above is the `uvm_field_int macro. In the transaction model one should add:


The UVM_ALL_ON flag in the macro instructs the code to consider each field for all built-in routines/methods like copy/clone/compare etc. We also suggest adding the post_randomize for ease of debug.

Now moving onto the 2nd question that the user asked: “Why does it print only 1 mismatch”?” – the built-in uvm_comparer has a field show_max that controls how many mismatches to show/display and its default value is 1. One could change it and set it to its maximum using SystemVerilog’s bit-fill operator ‘1. Now when we pass the modified comparator object to the compare() routine we will see al mismatches:


Sample output from Riviera-PRO is below:


Hope you find this hidden-gem nside uvm_comparator useful in your debug cycles. Have fund and contact us via in case you’ve a tough debug problem to crack.


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Making Verilog simulations a fun and useful game – welcome to EDAPlayground

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC

Ever wondered if you can run Verilog Sims from a Web Browser?

Well, playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground. EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free, and, since it is web-browser based, it runs on any OS. And you can be up and running in few minutes, without having to install EDA tools, licenses etc.

EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy — select the simulator on the option panel, and click Run.


If the sim creates a *.vcd wave dump, it is possible to view waves using EPWave browser-based viewer. To enable EPWave, simply set the following checkbox on the option panel:

Open EPWave after run

The wave window will open after the simulation completes.


EDA Playground has several code examples to play with, such as:

“Our short-term and international training attendees have always wanted a platform to run/play with simulations after the training sessions on their own, at their own schedule” says Mrs. Ajeetha Kumari, CEO of CVC Pvt Ltd. She continues “So far they had to install, manage their own tools or rely on their employers/universities to provide such a support; with the launch of EDA Playground this process can get simplified a lot in near future”.

To find out more about EDA Playground, watch the following video. Recommended viewing quality is 720p. EDAPlayground on You Tube

Victor Lyuboslavsky, Founder of Victor EDA

Technology partner, guest blogger at CVC

UVM-ML is here: Funcntional Verification is heterogeneous in nature – notes from DAC 2013

As part of my recent DAC 2013 minutes, here are some of the musings from customer experiences around DAC this year (and some from projects we have been doing in 2012-13 here).

While there is a large set of customers exploring SystemVerilog in its full capacity and with UVM, make no mistake – not many will throw away what has been done previously and that was precisely my talking point at DAC 2013 theater presentation earlier this June.

Below are some of the slides I presented to get you started:

And it is in this context the recently announced UVM-ML initiative from Accellera becomes very relevant to every verification team. It is still very much open and all of you can contribute to developing this to be useful to the verification community at large. You can learn more about this UVM-ML from this Cadence blog:

See you soon at UVM-ML conference calls/discussions.


DAC 2013 notes: Giraffes are everywhere, Verific inside story

As I recount on my recent DAC at Austin experince, one thing that surprised me was the number of Giraffes (sure, images/toys, wish the real ones..but I was at DAC and not a zoo/safari) in the exhibit floor.


Yes, am talking about the Verific’s mascot here. It was one of the tallest standing booths so not many could miss it. My friend Sashi Oblisetty led me to them after our early breakfast meeting that morning at DAC. I met with Michiel Ligthart, Verific’s president and chief operating officer. He is a tall man, a Netherlander/Dutch (Graag, ik kan een klien beetje Nederlands spreken .. –  Glad, I can speak a little bit Dutch language, thanks to my early days of work at Philips, Eindhoven). It was a pleasant surprise to see how many customers Verific has to-date, from their facebook page I found:

That’s impressive indeed. No wonder I found several small Giraffes on other vendors’ booth tables. It reminded me of the popular "Intel inside" campaign, perhaps Verific should do similar "Verific Inside" campaign in EDA world :-) Or should we call it "Giraffes are everywhere" (For those avid travellers, see:

I also met Ahbijit Chakraborty, their India GM (based out of Kolkata/Calcutta) and we agreed to follow-up on some of our DVAudit ideas post-DAC. If you wonder what DVAudit is, here is a brief on what I presented at Cadence theater at DAC floor, drop us a note via if you need more details.

Truly an engaging crew at Verific booth, we at TeamCVC do look forward to their PERL based parser front end to build custom utilities for our customers.


Out-of-the-box UVM experience with modern day EDA tools

It surprises me often how many young engineers (read “fresh graduates/Recent College Graduates”) struggle when it comes to the UNIX/GCC/Makefiles etc. I still recall our old IIT days when we did Yahoo/Altavista (Google wasn’t around back in 1996) search to resolve most of such issues and of-course use some common sense. 

Coming to the recent experience, as we were preparing for our recent demo at SNUG India 2013 DCE booth, I asked some of our young team members to run few UVM tests. When it came to the 11th hour preparations I got several error reports from these young engineers with various errors related to gcc/PATH etc. In our regular UVM training sessions the Makefiles exist so not much challenge in this regard. But when you ask these folks to create Makefile on their own to run UVM, things start getting interesting. A recent error message showed to me was:


recompiling module apb_subsystem_top
All of 30 modules done 

g++ -w -pipe -O -I/home/student/tools/eda/synopsys/vcs-mx_VE-2011.03-SP1-2/include \

-c /home/student/tools/uvm-1.1c/src/dpi/
/home/student/tools/uvm-1.1c/src/dpi/uvm_hdl.c: In function ‘int uvm_hdl_set_vlog(char*, \
t_vpi_vecval*, PLI_INT32)’:
/home/student/tools/uvm-1.1c/src/dpi/uvm_hdl.c:235: error: ‘vpi_release_handle’ was \
not declared in this scope

make[1]: *** [uvm_dpi.o] Error 1


A quick check with them revealed they were NOT really behind any custom UVM base library/version, any recent one would do. That led us to a much simpler fix – use the out-of-the-box UVM that gets shipped along with the modern day  EDA tools. For the starters, here are the 3 most popular tools and their options to run UVM out-of-the-box:

Cadence: IUS

irun -uvm -f file_list_with_your_src_files

The -uvm option will take care of all the include-dir and the DPI stuff needed to get UVM base-lib visible and usable for your code.

Synopsys: VCS

  vcs -ntb_opts uvm -f file_list_with_your_src_files 

The option -ntb_opts uvm takes care of the UVM base class for you! BTW, NTB stands for “Native TestBench” in VCS lingo.

Mentor: Questa

qverilog -f file_list_with_your_src_files

If you are wondering who takes of the “UVM” here – your most friendly EDA simulator does that “automatically” for you – the moment it “detects” uvm_pkg in your code. 

Sure you will need to learn how to use “customized UVM-lib” at times, but the above can well be a good start. Please note that the version of UVM could be different in different tools and even among different versions of the same tool (say IUS), but assuming you are just a beginner these details shouldn’t matter much to you to start with.

Good Luck with your UVM voyage!



Help yourself & UVM community by sparing few minutes – Verilab’s UVM survey


UVM Runtime Phasing and Phase Jumping Survey

If you are well aware of UVM runtime phasing/phase jumping issues, quickly help yourself and the UVM community at large by filling out this survey:

Now for a background and for those who are “undecided” whether or not I have an issue with it, here is more information:

One of the significant updates done to OVM while bringing up UVM as the standard for verification methodology was the phasing. (For a detailed paper on user issues with OVM phasing approach, see: and

As with any standard development, there are differing view points coming from various experts, users etc. around the globe.India being the most vibrant Verification geography, it is very probable that many of the verification leads here face these problems day-in and day-out. So why not speak up and help us fix the UVM phasing the way YOU would like it?

Verilab, a premier verification consulting firm based in the US is conducting a survey to find out whether UVM users are currently taking advantage of runtime phasing and phase jumps, and if so, whether or not they would be impacted by certain changes the committee might propose.

So in case you are an active user of UVM, please spare a few minutes and take the survey at:

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Easier PLI integration with MPSim

Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools.

For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples:

  1. NextOp/Atrenta’s BugScope 
  2. Novas’s Verdi/Debussy
  3. Axiom’s @Designer (Debugger that can work with all standard Verilog simulators)
  4. Trek from Brekersystems (
  5. OnPoint from

Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim ( ) provide a convenient TABLE format to ease this task. All you need to do is to create the following table:


And use standard gcc to compile your C-code as below:

gcc -m32 -pipe -c -g ../pr_tscale.c -I$(ATHDLROOT)/tb/incl –DAXIOM

Now, invoke the atsim compiler with the tab-file as shown in below command:

atsim -c ../pr_tscale.v +pliobj+../pr_tscale.o


For those trying it out at your end, notice the path to the *.o file should have “../” as the atsim compiled one-dir below (hidden dir).

Now if it was this simple, why would anyone FEAR  from it really? The answer is – that’s how the Verilog LRM defines it to be, see below if you have time and patience. Advanced verification platforms like MPSim will hide these details for you for your pleasure adn ease-of-use!

For those uninitiated with this fear, see how the Verilog LRM defines a data structure for this purpose below: (extract from standard vpi_user.h)




Now to use it in an end-user application such as the one found at: one needs to create a variable of this structure and fill in the integration details, see below:


If you managed to read up to this – then you are convinced that integration of VPI code isn’t for everyone – if not for tools like MPSim !

Good Luck!


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