Category Archives: Verilog

Making Verilog simulations a fun and useful game – welcome to EDAPlayground

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC

Ever wondered if you can run Verilog Sims from a Web Browser?

Well, playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground. EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free, and, since it is web-browser based, it runs on any OS. And you can be up and running in few minutes, without having to install EDA tools, licenses etc.

EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy — select the simulator on the option panel, and click Run.

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If the sim creates a *.vcd wave dump, it is possible to view waves using EPWave browser-based viewer. To enable EPWave, simply set the following checkbox on the option panel:

Open EPWave after run

The wave window will open after the simulation completes.

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EDA Playground has several code examples to play with, such as:

“Our short-term and international training attendees have always wanted a platform to run/play with simulations after the training sessions on their own, at their own schedule” says Mrs. Ajeetha Kumari, CEO of CVC Pvt Ltd. She continues “So far they had to install, manage their own tools or rely on their employers/universities to provide such a support; with the launch of EDA Playground this process can get simplified a lot in near future”.

To find out more about EDA Playground, watch the following video. Recommended viewing quality is 720p. EDAPlayground on You Tube

Victor Lyuboslavsky, Founder of Victor EDA

Technology partner, guest blogger at CVC

Mind the GAP – even in SystemVerilog macro definition

SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are:

  1. Added capability to extend the definition to multiple lines
  2. Added macros with arguments;
  3. Macro arguments can have default values too! (not fully supported by all tools though)

However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code.

Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with:

image

To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:

 

If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following
the name of the macro. The left parenthesis shall follow the text macro name immediately, with no space in
between.

In other words – as it is with any Metro station sign, you should be careful with the GAP/spaces :-)

image

Notice that “extra space” after the macro name CHECK1 is now gone! This works in Questa 10.2.

So next time when you code your macros – mind the GAP :-)

TeamCVC

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Easier PLI integration with MPSim

Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools.

For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples:

  1. NextOp/Atrenta’s BugScope 
  2. Novas’s Verdi/Debussy
  3. Axiom’s @Designer http://www.axiom-da.com (Debugger that can work with all standard Verilog simulators)
  4. Trek from Brekersystems (www.brekersystems.com)
  5. OnPoint from vennsa-da.com

Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim (http://www.axiom-da.com ) provide a convenient TABLE format to ease this task. All you need to do is to create the following table:

mpsim_tab

And use standard gcc to compile your C-code as below:

gcc -m32 -pipe -c -g ../pr_tscale.c -I$(ATHDLROOT)/tb/incl –DAXIOM

Now, invoke the atsim compiler with the tab-file as shown in below command:

atsim -c ../pr_tscale.v +tabfile+pr_tscale.tab +pliobj+../pr_tscale.o
./athdl_sv

 

For those trying it out at your end, notice the path to the *.o file should have “../” as the atsim compiled one-dir below (hidden dir).

Now if it was this simple, why would anyone FEAR  from it really? The answer is – that’s how the Verilog LRM defines it to be, see below if you have time and patience. Advanced verification platforms like MPSim will hide these details for you for your pleasure adn ease-of-use!

For those uninitiated with this fear, see how the Verilog LRM defines a data structure for this purpose below: (extract from standard vpi_user.h)

 

 vpi_systf

 

Now to use it in an end-user application such as the one found at: http://www.cvcblr.com/blog/?p=517 one needs to create a variable of this structure and fill in the integration details, see below:

vlog_startup

If you managed to read up to this – then you are convinced that integration of VPI code isn’t for everyone – if not for tools like MPSim !

Good Luck!

TeamCVC 

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Visualizing SystemVerilog event regions

One of the strengths of assertions in SystemVerilog is its well defined sampling semantics. Though it works out-of-the-box and is robust, many users don’t seem to understand it in depth. As we have been blogging on assertions – one needs to be very “pedantic”, i.e. detail oriented to be able to appreciate it, demonstrate it and understand it.

We at TeamCVC have been pioneering assertions as a focus area since our PSL book days (end of 2003, http://www.systemverilog.us/psl_info.html) and it has been almost a decade by now! We cover this in all our training sessions on assertions such as:

Even during our popular VSV course (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) we touch upon this topic during the program block discussion. Below is an extract from our training/book on SVA (http://www.systemverilog.us/sva_info.html):

 

SV_event_regions

 

While the above slide goes well into the depth of this topic, often users ask us if they could “visualize it” inside waveform. Recently we did a SVA class for a VHDL customer who use Questa. Being part of QVP http://www.mentor.com/products/fv/partners/qvp we at CVC have access to Mentor’s latest technologies and this customer insisted that we use Questa during the labs. We enabled more debug sessions including their famous Questa ATV (Assertion Thread Viewer) feature. One of the nice examples our TeamCVC have created explains the events/time-regions nicely. See below for a screenshot:

Picture1

 

It is almost the same as SystemVerilog LRM’s event Queue – brought inside the waveform, isn’t it! Here is a code snippet for the RTL regions such as “ACTIVE, INACTIVE & NBA” – this is same as in plain Verilog BTW:

rtl_regions

 

Now recall that in testbench with System Verilog there is a program block that executes in REACTIVE region. And so are the assertion action-blocks. And within program block one can do blocking, #0 and NBA ssigns. So how does that get scheduled?

Picture1

 

And relevant code-snippet for the REACTIVE assignments:

 

pgm_regions

 

Putting the full waveform:

Picture1

 

NOTE: the “time” doesn’t advance, it is only the DELTAs – Questa is powerful indeed in visualizing it, we will try and add other tool screenshots in near future if there is enough demand from you – our beloved readers!

Before we close, here is what a full, IDE (Integrated Development Environment) that Questa provides for this:

image

Hope you enjoyed this “flow of events” and the power of “visualizing” it – as much as we did. Drop your comments below!

Signing off with confidence, it is TeamCVC!

Verilog subtleties – $monitor vs. $display vs. $strobe

Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html 

He has adapted Murphy’s law into Verification as:

Applying to Verification (http://whatisverification.blogspot.in/2012/08/laws-and-verification.html )

Moore’s law – Amount of code to be verified doubles every 2 years.

Murphy’s law – Any code that isn’t verified will not work.

Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise!

Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe?

1. Usual answer: $monitor is “continuous monitoring” – Yes, good

For many fresh graduates the detail stops there – but not for those “verilog hungry, pedantic folks”. Here are some more:

1. $monitor & $strobe execute at the POSTPONED region of your Simulator’s event Q – read more about it in LRM or attend our detailed simulation/SVA training (http://www.cvcblr.com/trainings) for more details on this event queues etc.

2. With $display you may get more than display for the same time, for the same signals being displayed – but with $monitor you are guaranteed to get only one at any time for the same display list. As the LRM puts it:

 

(With $monitor being in use) If two or more arguments change value at the same time, only one display
is produced that shows the new values.
Only one $monitor display list can be active at any one time

The above can be little misleading statement – infact that was the case with our UNVERIFIED PPT slide with some code snippet. Here is a fixed example with some traces:

Consider the test vector setup as:

 Picture3

 

Notice that at time 100 we have “b” being assigned twice – one with BLOCKING and another NBA. With $monitor - you get only one display as guaranteed by LRM. However if we try mimicking the same with always block as below:

Picture6

 

Guess what – you get the display twice, see below:

 

Picture4

 

Now a more equivalent mimic would be to use $strobe instead of $display as in:

Picture5 

 

Now with SystemVerilog there are few more you could expand this topic to including:

1. Use always_comb instead of always @ (*) in the code above – it is guaranteed to wakeup at time 0

2. In the context of SVA (System Verilog Assertions), in 2009 the LRM added “deferred assertions” to handle similar situations.See: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=19966 and http://sv-verif.blogspot.in/2012/03/using-systemverilog-assertions-to-check.html

 

So that was good fun with “details” on what’s usually skipped as “simple stuff” during a Verilog training.  Below is full code incase you want to run, modify and experiment around:

Picture1

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Verilog PLI/VPI – a sample tree walker + hierarchical print_timescale app!

Here is a nice Verilog VPI (Verilog Procedural Interface a.k.a PLI 2.0) app that we mentioned during our just concluded Verilog training at CVC.

This application just walks through the complete design hierarchy and spits out the Timescale information for each module. It is quite handy to find which module has the least timescale precision value (and hence controls the whole simulation) for e.g. when the design has been given as a compiled database or a protected one – simple grep/PERL kind of ideas maynot fit. This application will extract:

  1. The module name
  2. Its Time Scale value
  3. Its TimePrecision value

Here is a PLI task named " $print_timescale " which if called on a top level module will print this information for the entire hierarchy.

The following Verilog code (which could be the top level of your design, or TB) shows how to use such a task.

 

vlog_topvlog_blk

 

Needless to say the hierarchy can be very deep and totally encrypted etc. It is all about tree traversal and printing the relevant portions of vpi_get as in:

Following is a code snippet from the VPI/PLI C-code:

vpi_c

 

Now wrap that inside a tree walker code that would walkdown your Verilog hierarchy (post elaboration) such as:

 

binary_tree_complete  

 

At each node, print the results.

results

 

Drop us a note in the comments below if you would like to see the complete VPI code listing!

 

Who said Verilog is simple – it can become very interesting with large designs with interesting challenges!

Now you see why CVC is in the best of Verification related technology when it comes to training engineers (freshers/experienced alike) – where else would engineers get to experiment and learn at their own pace all the way from UNIX, Verilog to SystemVerilog, Assertions, UVM and beyond? See http://www.cvcblr.com/trainings for more!

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