Category Archives: trainings

Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at:

Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:

  bit [7:0] msb_vec, lsb_vec;

msb_vec[7] = lsb_vec[0];
msb_vec[6] = lsb_vec[1];

// …

While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:

  msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic

But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator:

$display (” msb_vec: %b reverse: %b”, msb_vec, { << {msb_vec} } );

If the array was unppacked, there is a built-in array.reverse() available.

One of the good things about the modern, social media is we all stay connected atleast virtually – no matter where our careers take us to. In this case he is currently at Ahmedabad, Gujarat, India. So do feel free to contact us via for any SystemVerilog related help!

SystemVerilog-VMM to UVM migration – first step

In one of our recently concluded UVM training sessions at CVC a customer asked how easy is it to migrate an existing proven code base running with VMM to UVM. Since this is a very common situation, we at CVC have put together a detailed set of case studies and a half-a-day workshop on this topic. As a starting point we ask few simple questions to the customer on their code base so that we can provide an estimated effort involved in the migration. Invariably we start asking “Which VMM version do you run?” – and many are actually unaware :-( Here is a tiny piece of code that would get the answer right from your simulation:


A small VMM-built-in utility class is provided as part of VMM named vmm_version. It has few interesting methods, First one being:


The first one displays the major-minor versions such as 1.11 and vendor name. Typically EDA vendors customize these opensource libraries to add debug features and at times to fix incompatibilities across implementations. For instance when VMM was first released in opensource TeamCVC made it working on all EDA tools, fixing any Synopsys specific features in the VMM base class code. Then we donated it back to the community and other vendors did more changes. If you are interested in running it with Aldec’s Riviera-PRO feel free to contact us or directly

The other function that prints more information along with the “configurations  used to generate the VMM base code” is:     vmm_ver1

A sample output of the above from Aldec’s tool is below:


So in case you are migrating from VMM (or OVM) to UVM, call us for hints, case studies, or even better join our workshop on this topic.



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SystemVerilog UVM comparer – hidden gem in show_max

Recently a customer sought a help on how does the UVM’s built-in scoreboard mechanism works, specifically in_order and algorithmic comparators. While he was able to use them well in his design, it when things fail – i.e. he potentially found a design bug he needed additional assistance in debug. By default the UVM framework provides compare() routine for transaction/uvm_sequence_item. However unlike its predecessor HVLs such as the “E” language (IEEE 1647) or the OpenVera, System Verilog does not have the compare routine built-in to the language itself (for classes). Hence UVM adds it via base class and more. So when we have a transaction model such as:


Now by virtue of inheritance, a handy method my_xactn::compare is available.  So one can use it to compare 2 objects of this type as shown below:


Note: in the above code snippet the return value of compare is unused, in actual code of-course you should assert it/throw an `uvm_error etc.

Now, when we simulate this with Aldec’s Riviera-PRO here is what we see:


But now the user asked 2 good questions:

  • How does it know what to compare?
  • Why is printing only 1 mismatch and not all?

The answer to the first question above is the `uvm_field_int macro. In the transaction model one should add:


The UVM_ALL_ON flag in the macro instructs the code to consider each field for all built-in routines/methods like copy/clone/compare etc. We also suggest adding the post_randomize for ease of debug.

Now moving onto the 2nd question that the user asked: “Why does it print only 1 mismatch”?” – the built-in uvm_comparer has a field show_max that controls how many mismatches to show/display and its default value is 1. One could change it and set it to its maximum using SystemVerilog’s bit-fill operator ‘1. Now when we pass the modified comparator object to the compare() routine we will see al mismatches:


Sample output from Riviera-PRO is below:


Hope you find this hidden-gem nside uvm_comparator useful in your debug cycles. Have fund and contact us via in case you’ve a tough debug problem to crack.


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Quick start on ABV for VHDL designers – OVL + VHDL + Modelsim

Recently an ABV early stage user/explorer realized it is little hard to get started with OVL-VHDL-Modelsim combination. It surprised us as  it would many others in the industry, having known how well folks at Mentor have been supporting OVL, VHDL etc.

As valuable QVP partner with Mentor, we at TeamCVC decided to make it easier for end users. When we dug further we did realize it is not out-of-the-box. Hence we created a quick start example and uploaded it to our website.

Feel free to grab it from here: 

It is certainly a quick example just to demo the flow. Will add more soon. Here is the README for the example:

CVC’s OVL VHDL Example with Modelsim

To compile and run OVL VHDL example in Questa/MTI follow this example

We’ve used ovl_one_hot on a DUMMY signal, just to demo the flow.

You need latest OVL 2.7 release. We’ve included a part of that in this tar ball

To run
cd run_dir
make ovl

Still we strongly suggest VHDL users to choose PSL. But in case you need OVL, this example could help. Feel free to grab it from here: 

Send us your comments via

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Making Verilog simulations a fun and useful game – welcome to EDAPlayground

Victor Lyuboslavsky, Victor EDA, technology partner, guest blogger at CVC

Ever wondered if you can run Verilog Sims from a Web Browser?

Well, playing with Verilog and OVL has gotten a little easier recently thanks to the introduction of EDA Playground. EDA Playground is a web application that allows users to edit, simulate, share, and view waves for their HDL code. It is intended to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is free, and, since it is web-browser based, it runs on any OS. And you can be up and running in few minutes, without having to install EDA tools, licenses etc.

EDA Playground has two editor panes. The left one is intended for testbench code, and the right one intended for design code. The bottom pane is for simulation results, which are updated in real time when the simulation is running. Running a simulation is easy — select the simulator on the option panel, and click Run.


If the sim creates a *.vcd wave dump, it is possible to view waves using EPWave browser-based viewer. To enable EPWave, simply set the following checkbox on the option panel:

Open EPWave after run

The wave window will open after the simulation completes.


EDA Playground has several code examples to play with, such as:

“Our short-term and international training attendees have always wanted a platform to run/play with simulations after the training sessions on their own, at their own schedule” says Mrs. Ajeetha Kumari, CEO of CVC Pvt Ltd. She continues “So far they had to install, manage their own tools or rely on their employers/universities to provide such a support; with the launch of EDA Playground this process can get simplified a lot in near future”.

To find out more about EDA Playground, watch the following video. Recommended viewing quality is 720p. EDAPlayground on You Tube

Victor Lyuboslavsky, Founder of Victor EDA

Technology partner, guest blogger at CVC

Test your digital arithmetic – $urandom returns unsigned or signed?

SystemVerilog adds $urandom – a simple random number generator that returns a 32-bit UNSIGNED integer. Contrast it to good old $random – returns a 32-bit SIGNED integer.

Consider the below code snippet:

integer address;

initial begin : b1

  address = $urandom;

  $display (“%m address: %d”, address); end : b1

When you run the above code in Questa, one in a while you get:

# address = 90095195;

# address = -949724053;

First sight it looks strange, why is $urandom generating a negative number? Bug in the tool? Crazy? (See a real user post at:

A bit of thinking, taking eyes away from monitor screen would help – follow your basics on digital arithmetic:

  • integer – a signed 32-bit number (in Verilog)
  • i.e. holds−2(n−1) through 2(n−1)−1. (2’s complement representation)
  • So if you assign even a 32-bit UNSIGNED number with the MSB set to 1 – it will be treated as “signed 31-bits”
  • Hence –> $urandom does generate 32-bit UNSIGNED, but when you assign it to a 32-bit signed integer, be ready for a surprise.

Not convinced yet? We at CVC like that attitude – be rebellious. Try the below code yourself. Notice we made address a 33-bit signed number, run it for yourself in a good simulator.


Send your comments via for now (till we fix a hacker’s entry into our WP).


OTG – On-The-Go SystemVerilog tip: Assoc arrays – allocate OTG

Sparse arrays in general (in many computer languages) exhibit ‘allocate-on-the-go” behavior. System Verilog is no exception. During today’s VSV training at CVC we had some interesting discussion on this topic. SV assoc-arrays get allocated on-the-go, while it is well known and talked about fact – it is clear for the “write” to array. What about “read”? For some early stage users it is not so obvious that a $display is a reader as well. Consider the following piece of code (full code later):

logic [7:0] logic_aa [int];


  logic_aa[20] = 121;onthego

In the above code the 21st location gets allocated OTG, clear.

What about the following?

logic [7:0] logic_aa [int];


  $display (“%m CVC: read AA: “, logic_aa[20] );

What would you expect? Error? Or allocate OTG? Hold your answer, let’s see full code:

aa_1 onthego

Any guess? Well, the $display on an un-allocated assoc-array element is a reader too, hence gets allocated OTG (On-The-Go), default value gets assigned. Isn’t that somewhat “not so good”? Well, that’s why a good tool like Questa (from Mentor) emits a warning in such case, see below:


So next time when you use assoc-array ensure you recall this OTG behavior!

Safe journey with SV and CVC :-)


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Pinning down SystemVerilog program block

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother.

From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions (

Here comes a 2-minute run-down on this nice feature. Let’s look at some code:



Line 6: #10 DUT ‘reads” a signal named “sig_1”.

Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above)

Consider that the above “write” and “read” to the signal were done on “module” scope – this is potential “race” – as 2 different simulators can schedule these 2 initial blocks in arbitrary order. Such a race will be painful to debug, hard to migrate, harder to maintain etc. So how does bringing in program help here? Assuming you are familiar with System Verilog event scheduling mechanism (we cover this in detail during our SVA training – one would recall that there is a region named “REACTIVE” region that executes AFTER the “design” region/assignments. The program block code executes in this reactive region thereby avoiding the races by language! One could visualize this by running the code above in any SV tool. Here is a snapshot with Mentor’s Questa 10.2:



As you can see in the log/transcript, the “DUT” gets done first and then comes the TB/program block – all in same time-stamp though.

Now that being guaranteed to be consistent across EDA tools, users have one-less thing to worry about in their Verification journey.

Do send your comments via



Raise a few eyebrows with SVA’s $rose

Assertions have always been our passion at CVC. The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late.

In one of our recent, part-time SVA training session ( we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions:

"Things look bright when SVA syntax is discussed. it gets better when we start discussions"

One of the nice features in SVA in the ability to detect rising edge with $rose. It is quite simple to understand when applied on single bit signal. For non-startes, it is simply a change from 0 to 1. That’s true for a single bit. What about vectors? In the below code, consider “addr” signal as 4-bit vector (logic [3:0] addr;)

If you thought it is 0 to 1 as in decimal, you are straightaway in for a surprise. If you suspect it is “bitwise” ORing of all bits – you are over-thinking on this. Consider the trace below along with SVA result (with Cadence’s IUS & nice Simvision GUI)



Consider an example of 4-bit vector  and few transitions.


That’s the change of LSB from 0 to 1 is really $rose.

Now consider the below transitions:


i.e. not every other bit counts here – only the change in LSB is considered. Did that raise an “eyebrow”?

Now consider an ascending order of “addr” values: (0 –>1 –> 2 -> 3 –> 4..)


Note that every alternate transition causes the $rose to be true, indicated by the “failed” notification in Simivision above – recall the system verilog assertion as:

$rose (addr) |-> 1’b0; // flag a failure, make it visible

Make no mistake, the $rose doesn’t work on “strictly ascending” consider few more traces below:


Now to raise few more eyebrows, consider the below trace with “descending” series of addr values:


So while a simplistic view of “0 to 1” is “ascending/increment”, the $rose is different when it is applied on a vector, even “descending/decrementing” transitions trigger $rose.

Now to summarize: $rose –> EVEN to ODD change :-)

Want to learn more SVA tricks, drop us a note via to know about our next SVA training session in Bangalore.

Signing off,


Out-of-the-box UVM experience with modern day EDA tools

It surprises me often how many young engineers (read “fresh graduates/Recent College Graduates”) struggle when it comes to the UNIX/GCC/Makefiles etc. I still recall our old IIT days when we did Yahoo/Altavista (Google wasn’t around back in 1996) search to resolve most of such issues and of-course use some common sense. 

Coming to the recent experience, as we were preparing for our recent demo at SNUG India 2013 DCE booth, I asked some of our young team members to run few UVM tests. When it came to the 11th hour preparations I got several error reports from these young engineers with various errors related to gcc/PATH etc. In our regular UVM training sessions the Makefiles exist so not much challenge in this regard. But when you ask these folks to create Makefile on their own to run UVM, things start getting interesting. A recent error message showed to me was:


recompiling module apb_subsystem_top
All of 30 modules done 

g++ -w -pipe -O -I/home/student/tools/eda/synopsys/vcs-mx_VE-2011.03-SP1-2/include \

-c /home/student/tools/uvm-1.1c/src/dpi/
/home/student/tools/uvm-1.1c/src/dpi/uvm_hdl.c: In function ‘int uvm_hdl_set_vlog(char*, \
t_vpi_vecval*, PLI_INT32)’:
/home/student/tools/uvm-1.1c/src/dpi/uvm_hdl.c:235: error: ‘vpi_release_handle’ was \
not declared in this scope

make[1]: *** [uvm_dpi.o] Error 1


A quick check with them revealed they were NOT really behind any custom UVM base library/version, any recent one would do. That led us to a much simpler fix – use the out-of-the-box UVM that gets shipped along with the modern day  EDA tools. For the starters, here are the 3 most popular tools and their options to run UVM out-of-the-box:

Cadence: IUS

irun -uvm -f file_list_with_your_src_files

The -uvm option will take care of all the include-dir and the DPI stuff needed to get UVM base-lib visible and usable for your code.

Synopsys: VCS

  vcs -ntb_opts uvm -f file_list_with_your_src_files 

The option -ntb_opts uvm takes care of the UVM base class for you! BTW, NTB stands for “Native TestBench” in VCS lingo.

Mentor: Questa

qverilog -f file_list_with_your_src_files

If you are wondering who takes of the “UVM” here – your most friendly EDA simulator does that “automatically” for you – the moment it “detects” uvm_pkg in your code. 

Sure you will need to learn how to use “customized UVM-lib” at times, but the above can well be a good start. Please note that the version of UVM could be different in different tools and even among different versions of the same tool (say IUS), but assuming you are just a beginner these details shouldn’t matter much to you to start with.

Good Luck with your UVM voyage!