Verification pioneers do it again – welcome to Advanced Specman

Srinivasan Venkataraman, Chief Technology Officer, CVC Pvt Ltd (www.cvcblr.com)

TeamSpecman representatives for this Blog interview: Kishore Karnane, Adam Sherer, Hannes Froehlich, and Ariel Melchior

During recent ClubT India session I met the famous “TeamSpecman (www.twitter.com/teamspecman )” to see what’s new about Specman/e and general verification roadmap from them. To my pleasant surprise they offered much more than what I got to know from regular eWG updates (CVC is part of the eWG @ www.ieee1647.org to contribute & stay on top of the upcoming language updates therein). The Incisive team has joined hands with the Specman team to roll out the “Specman Advanced Option” for power users of verification. Now, just around DAC time, I got a chance to interview the “TeamSpecman” including some of their core R&D folks to delve a little deep into the motivation behind the updates, some of them being rolled out and others in pipeline. What resulted is the following interactive Q&A session, sit back and enjoy..and welcome to Advanced Specman!

TeamCVC: Hello Gentlemen, welcome to this interactive, Q&A blog – an innovative style of introducing some cool technologies. Having been pioneers in the field of verification ever since the early days of introducing constrained-random, coverage-driven verification to OVM-e multi-language era – you folks have been locked onto some of the toughest verification challenges. With so much focus on languages for verification, what do you have in store for the DV community up-next?

TeamSpecman: On the verification front, Cadence is introducing many new and enhanced technologies at DAC this year. For example,

· Cadence Incisive Specman Elite supports the world’s most advanced verification users with the unique aspect-oriented features of the e language. It has a new Specman Advanced Option available that adds advanced debug and performance features, including multi-core support.

· Cadence Incisive Enterprise Simulator (IES) has added support for the Universal Verification Methodology (UVM), the emerging Accellera standard, new low-power and debug features as well as an Incisive Advanced Option for multi-core performance.

· Cadence Incisive Enterprise Verifier (IEV) is a new verification desktop product with simulation, formal, and dual-engine modes. It includes all the simulation features of Incisive Enterprise Simulator and all the formal features of Incisive Formal Verifier.

· Cadence Incisive Enterprise Manager (IEM) enables automated verification planning, runs tools on a server farm, and collects metrics across these runs to judge verification completeness.

As part of the Cadence EDA360 vision, we will be discussing these technologies in much more detail at DAC this year. We encourage you to stop by the Cadence Booth 1334, Hall B from June 14th – 16th in Anaheim, CA

TeamCVC: Some of the most advanced DV teams across the globe have been using Specman for years with millions of lines of e-code in existence and they are looking for “more out-of-the-box” performance. More so, with the languages (e & SystemVerilog) for verification have been standardized, it is key to see how users can leverage on multi-language, multi-vendor/simulator environments. For instance with a typical code base of 25K+ lines of e-code, the performance of compiler is becoming a limiting factor in the overall productivity of the DV team.

The good news though is, on the compute infrastructure side, multi-core machines have become very affordable with 2, 4, 6 or even 8-core CPUs occupying every user’s desktops. How does one leverage on this in day-to-day DV tasks?

TeamSpecman: Srini, yes, this has been one of the most requested enhancements from our Specman/e customers. So, the good news is that the Specman Advanced Option does allow the customer to leverage the multi-core servers during the compilation mode. We have already seen significant performance improvements with this newly added functionality. We are seeing close to xN (N= # cores) speedup in compilation time. In other words, we have seen that the performance improvement very nicely scales linearly through 8 cores but then the shared memory management in the underlying CPU architecture causes sub linear scaling beyond 8 cores.

TeamCVC: So in short, my compiles can be as fast as that of number of cores on my server? That’s exciting as it can easily cut down our development cycles, debug cycles etc.

TeamSpecman: That is correct. We have been seeing linear scaling in performance. It is very exciting!!

TeamCVC: When one talks of compiled code, a pressing issue has been the debug or the lack of it, I must say. While we all love high performance simulations, the limited debug-ability of compiled code has been a constant source of pain. What are your plans on that front?

TeamSpecman: Srini, yes, debugging complied code can be a pain. That is why we have added another new functionality in the Specman Advanced Option. This new feature will enable e source line debug of compiled code. This will reduce the overhead of maintaining different flows for debug and regression runs. The customers will be able to just run in the compiled mode all the time and be able to set a breakpoint in their compiled code for easy debug. This functionality will be available in the Q4 timeframe. Overall, this can improve the overall performance up to 2x.

TeamCVC: WoW! So now I can set a BP (breakpoint) *anywhere* in my compiled e -code and do “step..step..step” from there on – am I hearing it correctly or am I day-dreaming here?

TeamSpecman: You are definitely hearing it correctly. This is no longer a dream. It will be a reality very soon in the Incisive 10.2 release. We are looking for some customers who would like to beta-test this functionality in their verification environment.

TeamCVC: Here is another common scenario – with complex designs like large processors, packet engines, the initialization/setup/boot sequence takes significant time. All tests are running through similar initial stage that can be saved and later on restored in order to trigger the ‘interesting’ scenarios , either by running different seed or by loading new test. How do you foresee this challenge to be addressed in wider context?

TeamSpecman: We address this limitation again in the Specman Advanced Option by enabling the customer to leverage the “restore” command that allows users to start a new random test from a saved state post simulation start. In other words, we will provide the ability to run until some point, save the state, start the test from the saved point using different seed or load another e test. This has been confirmed by customers that can enable them savings of over 60% productivity improvement

TeamCVC: This is a high-voltage feature for sure with potentially several takers hungrily waiting for it. Where can we find more information about this?

TeamSpecman: Yes, every time we present this functionality to a customer, their eyes light up since they can see the significant time savings with functionality. The gain heavily depends on the length of the bring-up time (reset) of the environment. The typical estimation is about 50-60% while there are customers that have estimated it even higher. So, as you can see, instead of tweaking the simulator to squeeze another 5 – 10% performance improvement, “e” is going to leapfrog over the currently available HDL simulator performance. Again, we would love to find customers who are interested in beta testing this functionality too. This functionality will be available in the Incisive 10.2 release. We would recommend that customers contact their local Cadence Sales Representative to get more details.

TeamCVC: Given all these “advanced” capabilities, tell me something – am I Cadence-limited to avail these benefits or can I still use another HDL simulator with Specman for the testbench part?

TeamSpecman: That’s the beauty of this new option. It works with either use model. The customer can use Specman as part of the Incisive Enterprise Simulator (IES-XL) or they can use it as a standalone product with a 3rd party simulator. So, this new option will work with VCS and Questa simulators too. In other words, customers will not be Cadence-limited.

TeamCVC: What are your thoughts on extending these capabilities to SystemVerilog based solution as well?

TeamSpecman: We at Cadence are committed to supporting all standards for our customers. Given the vast user base of matured and advanced verification users in Specman, it makes perfect sense for us to invest heavily in Specman/e. Infact it serves as the perfect platform for us to introduce, test-drive some of these advanced capabilities with Specman – simply because there is a large base of existing e-code that demand such power. Once we get enough feedback and the technology with other languages advance to where e is today, we are committed to make them available there too – at the end of the day the customers have their way and we at Cadence are committed to making our customers successful.

TeamCVC: So, to summarize things – as a long term Specman user put it during ClubT Bangalore, “Specman made industry realize functional verification as an engineering discipline on its own”. Having pioneered verification for over a decade, it is time for them to go beyond just the language and IPs and enable users to be more productive! Thanks gentlemen for your time and more importantly YOU – the readers having gotten so far. Feel free to add your comments right here @ www.cvcblr.com/blog or if you are at DAC, stop by the Cadence Booth 1334, Hall B from June 14th – 16th.

BTW, CVC’s flagship -course is out and is called “EssentialE” – targeted at beginners with an advanced eVC level course being in the works. Checkout www.cvcblr.com/trainings for updates!