Many articles, discussions have, in the last few years declared the most powerful verification language, IEEE-1647, the E-language as “dead” in favor of SystemVerilog. While it is very clear “SystemVerilog” is step-up from Verilog and hence is an easier next step for Verilog/HDL based verification folks, it is far from replacing well established, and still growing capabilities of E – arguably the most powerful language to do verification of HDL designs.
With recent surge in Specman based jobs especially in India we were curious to see what’s happening. Here is what we found:
New Project starts with Specman
- To give first hand information, we at CVC (www.cvcblr.com) have recently started a customer verification project, from scratch using Specman to verify a new RTL design block.
- We also heard from Singapore that they have interns starting their projects in Specman. From industry/ecosystem point of view, internship is generally for future projects especially if they are on advanced topics.
- Specman based co-verification project recently done at TI India, see brief at: http://in.linkedin.com/pub/karthikeyan-b/19/a21/642
- IEEE 1647-2011 updates: http://www.cvcblr.com/blog/?p=333
The Job scenario/market
Most of the verification jobs in recent times have asked for Specman and/or SystemVerilog experts. Given the history of Specman in India it is natural to find more Specman engineers though lot many engineers are getting trained and deployed in SystemVerilog, our VSV (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf) training classes are selling hot cakes for the last 4 years!
What is really interesting is over the last few weeks there has been a sudden increase in Specman aware engineers from various Deisgn service providers in India. This is a very clear change in trend compared to last few years. Also we have more training queries coming to CVC on Specman/eRM/UVM-e – mostly from experienced engineers; another indicator of the sudden market change.
More than just Cadence/Specman supporting E?
Perhaps this would be the single most reason why many believe E is/was dying – it is a single vendor, but based on John Cooley’s time trusted ESNUG article, that maynot be true anymore, see:
Subject: Reader seeks user's reviews of SNPS/MENT support for Specman "e"
Also his previous post on related topic: http://www.deepchip.com/items/0488-05.html
So at the close of 2011, the “Badshaah/King of Functional Verification language – IEEE-1647 is perhaps rejuvenating and coming stronger into 2012!
Technical background information
Perhaps the most recent one on technical front is the proposed UVM ML – Multi-language donation from Cadence to Accellera, see: http://www.uvmworld.org/contributions-details.php?id=98&keywords=UVM_ML
In case you need deep technical articles.papers/webinars on this, see:
IEEE 1647-2011 updates: http://www.cvcblr.com/blog/?p=333
E vs. SV technical comparison: http://www.cadence.com/rl/Resources/conference_papers/Apples_versus_apples_HVL_cp.pdf
Webinar on Specman vs. SystemVerilog: http://www.cadence.com/Community/blogs/ii/archive/2011/09/21/webinar-seeks-to-end-the-debate-e-or-systemverilog.aspx