Verification inter-operability beyond UVM

As industry gets ready for adopting UVM with SystemVerilog, there are several practical combinations that come to the fore. One of the important concerns is about the existing code base/VIPs that can be “reused as-is”, yet benefit from various UVM features. For instance consider a VMM based VIP being plugged into a new UVM based env. Several user requirements/expectations arise:

1. Can the UVM & VMM co-exist in same simulation?

2. Can we leverage on single messaging scheme – instead of both `uvm_error & `vmm_error counting on their own, how do we unify them?

3. Can UVM phasing control/synchronize the vmm_xacotr::start/stop_xactor?

4. How does the UVM-Objection work with VMM-Consensus?

5. How do we talk from VMM-channel to UVM components and vice-versa?

6.How does the UVM ACTIVE/PASSIVE mechanism control VMM xactors underneath?

7. Does UVM config mechanism affect the VMM, if yes, how, if not then what do we do?

I am sure there are more. But just enough to get you worried! Thankfully the problem seems to have been acknowledged by the EDA vendors and potential solutions have started emerging. For instance the recently released VMM/UVM inter-op kit from Synopsys is at:


Another common requirement from many customers is the ability to mix multiple modeling & verification languages with UVM. Cadence recently donated its version of UVM ML (Multi-Language) to Accellera for potential extension. This contains UVM-SystemC via TLM 2,0 and UVM-e for integrating IEEE 1647-E based eVCs to UVM. Though the industry has publically seen only Cadence’s Specman supporting IEEE 1647-E language, if John’s ESNUG were to be trusted (why not BTW?, see:, it may be soon that all major vendors release E-support.

As noted in our recent blog, the upcoming 2012 year seems to be quite interesting for Verification technologies.

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