As we get to the end of an eventful 2013 and look forward to a great 2014, TeamCVC is at Manipal, a beautiful coastal town in the West coast of India. Surrounded by Arabian sea coast on one side and Western Ghats on the other, this is the ideal place for a peaceful research center and it is no co-incidence that the famous Manipal University is housed here.
Coming to this town and conducting a 10-day boot-camp on SystemVerilog and UVM has been a pleasure so far as we have a young, talented, enthusiastic set of attendees. One thing that we continuously get asked during our VSV training sessions is – which SystemVerilog LRM to refer to? While the Google search reveals several PDFs, it gets quite confusing to a newcomer which one to pickup and refer to. In the past it used to be the due to “lack of reliable, legal reference” as the IEEE LRM was available at a cost. However the IEEE 1800-2012 LRM got released for free of cost, thanks to the IEEE GIT program. So go ahead and get a legal, personal copy of the SystemVerilog LRM for free from:
The added benefit of this updated LRM is that you also are ready embrace the latest features of this ever expanding language. As a tailpiece information, TeamCVC is delivering a half-day tutorial at IIT Mumbai as part of VLSI Design Conference 2014, so join us on Sunday, Jan 15th at IIT Mumbai if you want to get latest SV 2012 features explained with CVC’s renowned quality trainers!