Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at: http://goo.gl/oq4FmF

Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:

  bit [7:0] msb_vec, lsb_vec;

msb_vec[7] = lsb_vec[0];
msb_vec[6] = lsb_vec[1];

// …

While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:

  msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic

But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator:

$display (” msb_vec: %b reverse: %b”, msb_vec, { << {msb_vec} } );

If the array was unppacked, there is a built-in array.reverse() available.

One of the good things about the modern, social media is we all stay connected atleast virtually – no matter where our careers take us to. In this case he is currently at Ahmedabad, Gujarat, India. So do feel free to contact us via info@cvcblr.com for any SystemVerilog related help!