VHDL + PSL action blocks – quick guide

For those VHDL folks exploring advanced verification techniques such as ABV (Assertion Based Verification), here is some trick for you all! A many of you would be aware VHDL 2008 standard incorporated IEEE 1850 PSL (VHDL flavor) in it and much before that EDA tools supported PSL + VHDL as a good combination. One of the earliest tutorials on PSL and most widely read one is available @ http://www.project-veripage.com/psl_tutorial_1.php and was authored by our CEO Mrs. Ajeetha Kumari.

As it can be seen in the tutorial PSL makes ABV adoption really simple and effective and leads to immediate benefits to the design verification cycle. One of the not-so-uncommon requirements from user community of VJDL + PSL is the ability to refer to PSL events/status from within VHDL Testbench code. This could then be used for PASS/AIL detection, coverage etc. A nice trick in PSL is to use “endpoints”.  Now coming to specific syntax, there are2 variants – in Accellera version of PSL, endpoint was a keyword as shown in ode below. This feature works like charm in most of the EDA tools. However in IEEE 1850 version of PSL, this has been replaced with ended() method. We will focus on endpoint in this example, but do try the alternate if your tool already supports it.

psl_ep

Basic idea is to use the endpoint to detect end of  a desired sequence of temporal and that now becomes an implicit boolean inside the underlying HDL framework (VHDL in this case).

A broader scope would be to expand this capability to assert/cover etc. There is a proposal for it at; http://www.eda.org/twiki/bin/view.cgi/P1076/PslAttributes but NOT approved/implemented by tools yet. Start adding your view in that TWIKI page and push your vendor for supporting the same.

TeamCVC

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Asynchronous events and SVA – a quick primer

During our recent SystemVerilog Assertions update webinar (http://www.cvcblr.com/blog/?p=802) one of the audience raised a question on how to check asynchronous events using SVA. Here comes a quick response with code. Also simulated using Aldec’s Riviera-PRO tool.

sva_async

 

As you can see in the picture, no clock involved per-se, but use the start and end events themselves as clock for the SVA.

So, if you’ve more challenging requirements, do drop in at CVC and we will assist you resolve them!

TeamCVC

Catch-up with SVA 2009-2012 updates – free Webinar on Oct 31st

Simplified Assertion Adoption with SystemVerilog 2012 (EU/ASIA)

Date: Thursday, October 31st, 2013

Time: 2:00 PM-3:00 PM IST – India time / 9:30 AM-10:30 AM CET (European time)       

Host: Aldec, CVC’s valued EDA partner (www.aldec.com)
Presented by: Srinivasan Venkataramanan (http://www.linkedin.com/in/svenka3)

                       CVC (Contemporary Verification Consultants www.cvcblr.com) – Aldec’s Training Partner,

Assertions have been in use for over a decade for now, however, writing detailed, temporal expressions in plain SystemVerilog (SV) 2005 has been at times a demanding task for first time users. While it gets easier as users mature with SVA, the language has made it more straightforward to express complex temporals with recent additions to the standard.

With SV 2012 LRM becoming freely available to all users, the adoption is expected to grow much faster. This webinar will demonstrate some of the important LTL operators added to the SVA such as until, eventually, etc. Using real-life case studies, the presenter demonstrates how these new operators can significantly reduce complexity of SVA coding. Attendees will be taken through a small, real-life protocol and shown how to break down the requirements in an “edge-by-edge” approach to coding SVA. An Ethernet-like protocol case study will be used to demonstrate the value of assertions while building driver BFMs in UVM. This clearly highlights the benefit of adding assertions upfront in a project cycle by helping reduce the TB development time.

This is a FREE webinar, but registration is required. Choose your slot depending on your geography.

India/Asia/Europe: http://www.aldec.com/en/events/338

USA/Rest Of the World: http://www.aldec.com/en/events/339

Test your digital arithmetic – $urandom returns unsigned or signed?

SystemVerilog adds $urandom – a simple random number generator that returns a 32-bit UNSIGNED integer. Contrast it to good old $random – returns a 32-bit SIGNED integer.

Consider the below code snippet:

integer address;

initial begin : b1

  address = $urandom;

  $display (“%m address: %d”, address); end : b1

When you run the above code in Questa, one in a while you get:

# address = 90095195;

# address = -949724053;

First sight it looks strange, why is $urandom generating a negative number? Bug in the tool? Crazy? (See a real user post at: http://goo.gl/yp0WZ)

A bit of thinking, taking eyes away from monitor screen would help – follow your basics on digital arithmetic:

  • integer – a signed 32-bit number (in Verilog)
  • i.e. holds−2(n−1) through 2(n−1)−1. (2’s complement representation)
  • So if you assign even a 32-bit UNSIGNED number with the MSB set to 1 – it will be treated as “signed 31-bits”
  • Hence –> $urandom does generate 32-bit UNSIGNED, but when you assign it to a 32-bit signed integer, be ready for a surprise.

Not convinced yet? We at CVC like that attitude – be rebellious. Try the below code yourself. Notice we made address a 33-bit signed number, run it for yourself in a good simulator.

image

Send your comments via info@cvcblr.com for now (till we fix a hacker’s entry into our WP).

TeamCVC

OTG – On-The-Go SystemVerilog tip: Assoc arrays – allocate OTG

Sparse arrays in general (in many computer languages) exhibit ‘allocate-on-the-go” behavior. System Verilog is no exception. During today’s VSV training at CVC we had some interesting discussion on this topic. SV assoc-arrays get allocated on-the-go, while it is well known and talked about fact – it is clear for the “write” to array. What about “read”? For some early stage users it is not so obvious that a $display is a reader as well. Consider the following piece of code (full code later):

logic [7:0] logic_aa [int];

initial

  logic_aa[20] = 121;onthego

In the above code the 21st location gets allocated OTG, clear.

What about the following?

logic [7:0] logic_aa [int];

initial

  $display (“%m CVC: read AA: “, logic_aa[20] );

What would you expect? Error? Or allocate OTG? Hold your answer, let’s see full code:

aa_1 onthego

Any guess? Well, the $display on an un-allocated assoc-array element is a reader too, hence gets allocated OTG (On-The-Go), default value gets assigned. Isn’t that somewhat “not so good”? Well, that’s why a good tool like Questa (from Mentor) emits a warning in such case, see below:

aa_2

So next time when you use assoc-array ensure you recall this OTG behavior!

Safe journey with SV and CVC :-)

TeamCVC 

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Pinning down SystemVerilog program block

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother.

From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions (http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf).

Here comes a 2-minute run-down on this nice feature. Let’s look at some code:

 

PGM_1

Line 6: #10 DUT ‘reads” a signal named “sig_1”.

Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above)

Consider that the above “write” and “read” to the signal were done on “module” scope – this is potential “race” – as 2 different simulators can schedule these 2 initial blocks in arbitrary order. Such a race will be painful to debug, hard to migrate, harder to maintain etc. So how does bringing in program help here? Assuming you are familiar with System Verilog event scheduling mechanism (we cover this in detail during our SVA training – http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) one would recall that there is a region named “REACTIVE” region that executes AFTER the “design” region/assignments. The program block code executes in this reactive region thereby avoiding the races by language! One could visualize this by running the code above in any SV tool. Here is a snapshot with Mentor’s Questa 10.2:

PGM_2

 

As you can see in the log/transcript, the “DUT” gets done first and then comes the TB/program block – all in same time-stamp though.

Now that being guaranteed to be consistent across EDA tools, users have one-less thing to worry about in their Verification journey.

Do send your comments via training@cvcblr.com

Regards

TeamCVC

Raise a few eyebrows with SVA’s $rose

Assertions have always been our passion at CVC. The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late.

In one of our recent, part-time SVA training session (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions:

"Things look bright when SVA syntax is discussed. it gets better when we start discussions"

One of the nice features in SVA in the ability to detect rising edge with $rose. It is quite simple to understand when applied on single bit signal. For non-startes, it is simply a change from 0 to 1. That’s true for a single bit. What about vectors? In the below code, consider “addr” signal as 4-bit vector (logic [3:0] addr;)

If you thought it is 0 to 1 as in decimal, you are straightaway in for a surprise. If you suspect it is “bitwise” ORing of all bits – you are over-thinking on this. Consider the trace below along with SVA result (with Cadence’s IUS & nice Simvision GUI)

 

rose2

Consider an example of 4-bit vector  and few transitions.

rose6

That’s the change of LSB from 0 to 1 is really $rose.

Now consider the below transitions:

rose5

i.e. not every other bit counts here – only the change in LSB is considered. Did that raise an “eyebrow”?

Now consider an ascending order of “addr” values: (0 –>1 –> 2 -> 3 –> 4..)

image

Note that every alternate transition causes the $rose to be true, indicated by the “failed” notification in Simivision above – recall the system verilog assertion as:

$rose (addr) |-> 1’b0; // flag a failure, make it visible

Make no mistake, the $rose doesn’t work on “strictly ascending” consider few more traces below:

rose7

Now to raise few more eyebrows, consider the below trace with “descending” series of addr values:

image

So while a simplistic view of “0 to 1” is “ascending/increment”, the $rose is different when it is applied on a vector, even “descending/decrementing” transitions trigger $rose.

Now to summarize: $rose –> EVEN to ODD change :-)

Want to learn more SVA tricks, drop us a note via training@cvcblr.com to know about our next SVA training session in Bangalore.

Signing off,

TeamCVC 

UVM-ML is here: Funcntional Verification is heterogeneous in nature – notes from DAC 2013

As part of my recent DAC 2013 minutes, here are some of the musings from customer experiences around DAC this year (and some from projects we have been doing in 2012-13 here).

While there is a large set of customers exploring SystemVerilog in its full capacity and with UVM, make no mistake – not many will throw away what has been done previously and that was precisely my talking point at DAC 2013 theater presentation earlier this June.

Below are some of the slides I presented to get you started:

And it is in this context the recently announced UVM-ML initiative from Accellera http://www.accellera.org/apps/org/workgroup/mlwg/ becomes very relevant to every verification team. It is still very much open and all of you can contribute to developing this to be useful to the verification community at large. You can learn more about this UVM-ML from this Cadence blog:  http://bit.ly/14IdjrA

See you soon at UVM-ML conference calls/discussions.

TeamCVC

DAC 2013 notes: Giraffes are everywhere, Verific inside story

As I recount on my recent DAC at Austin experince, one thing that surprised me was the number of Giraffes (sure, images/toys, wish the real ones..but I was at DAC and not a zoo/safari) in the exhibit floor.

 

Yes, am talking about the Verific’s mascot here. It was one of the tallest standing booths so not many could miss it. My friend Sashi Oblisetty led me to them after our early breakfast meeting that morning at DAC. I met with Michiel Ligthart, Verific’s president and chief operating officer. He is a tall man, a Netherlander/Dutch (Graag, ik kan een klien beetje Nederlands spreken .. –  Glad, I can speak a little bit Dutch language, thanks to my early days of work at Philips, Eindhoven). It was a pleasant surprise to see how many customers Verific has to-date, from their facebook page I found:

That’s impressive indeed. No wonder I found several small Giraffes on other vendors’ booth tables. It reminded me of the popular "Intel inside" campaign, perhaps Verific should do similar "Verific Inside" campaign in EDA world :-) Or should we call it "Giraffes are everywhere" (For those avid travellers, see: http://bit.ly/11GNP8B)

I also met Ahbijit Chakraborty, their India GM (based out of Kolkata/Calcutta) and we agreed to follow-up on some of our DVAudit ideas post-DAC. If you wonder what DVAudit is, here is a brief on what I presented at Cadence theater at DAC floor, drop us a note via info@cvcblr.com if you need more details.

Truly an engaging crew at Verific booth, we at TeamCVC do look forward to their PERL based parser front end to build custom utilities for our customers.

Srini

Out-of-the-box UVM experience with modern day EDA tools

It surprises me often how many young engineers (read “fresh graduates/Recent College Graduates”) struggle when it comes to the UNIX/GCC/Makefiles etc. I still recall our old IIT days when we did Yahoo/Altavista (Google wasn’t around back in 1996) search to resolve most of such issues and of-course use some common sense. 

Coming to the recent experience, as we were preparing for our recent demo at SNUG India 2013 DCE booth, I asked some of our young team members to run few UVM tests. When it came to the 11th hour preparations I got several error reports from these young engineers with various errors related to gcc/PATH etc. In our regular UVM training sessions the Makefiles exist so not much challenge in this regard. But when you ask these folks to create Makefile on their own to run UVM, things start getting interesting. A recent error message showed to me was:

 

recompiling module apb_subsystem_top
All of 30 modules done 

g++ -w -pipe -O -I/home/student/tools/eda/synopsys/vcs-mx_VE-2011.03-SP1-2/include \

-c /home/student/tools/uvm-1.1c/src/dpi/uvm_dpi.cc
/home/student/tools/uvm-1.1c/src/dpi/uvm_hdl.c: In function ‘int uvm_hdl_set_vlog(char*, \
t_vpi_vecval*, PLI_INT32)’:
/home/student/tools/uvm-1.1c/src/dpi/uvm_hdl.c:235: error: ‘vpi_release_handle’ was \
not declared in this scope

make[1]: *** [uvm_dpi.o] Error 1

 

A quick check with them revealed they were NOT really behind any custom UVM base library/version, any recent one would do. That led us to a much simpler fix – use the out-of-the-box UVM that gets shipped along with the modern day  EDA tools. For the starters, here are the 3 most popular tools and their options to run UVM out-of-the-box:

Cadence: IUS

irun -uvm -f file_list_with_your_src_files

The -uvm option will take care of all the include-dir and the DPI stuff needed to get UVM base-lib visible and usable for your code.

Synopsys: VCS

  vcs -ntb_opts uvm -f file_list_with_your_src_files 

The option -ntb_opts uvm takes care of the UVM base class for you! BTW, NTB stands for “Native TestBench” in VCS lingo.

Mentor: Questa

qverilog -f file_list_with_your_src_files

If you are wondering who takes of the “UVM” here – your most friendly EDA simulator does that “automatically” for you – the moment it “detects” uvm_pkg in your code. 

Sure you will need to learn how to use “customized UVM-lib” at times, but the above can well be a good start. Please note that the version of UVM could be different in different tools and even among different versions of the same tool (say IUS), but assuming you are just a beginner these details shouldn’t matter much to you to start with.

Good Luck with your UVM voyage!

TeamCVC

 

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